February 2005 Exclusive Feature #2:

Factoring the environment into wafer fab conversions

By Tom Cooper, Tim Higgs, John Harland, Terrence J. McManus*, Intel Corp., Chandler, Arizona

Increasingly, semiconductor manufacturing hurdles are being addressed with new materials and wafer processing techniques that present ever changing environmental challenges. However, process changes and the introduction of larger 300mm wafers also open up the opportunity to re-engineer facilities and greatly improve environment protection. Here’s how Intel’s “Design for the Environment” (DfE) program targets step-function improvements in the transition to 300mm fabs and next-generation processes.

Each shrink in device feature size represents a new process and an opportunity to improve the environmental performance of manufacturing. The emphasis of Intel’s Design for the Environment (DfE) Program focuses on specific tools and processes to reduce emissions, water use, chemical use and/or energy consumption. These improvements are often incremental. When wafer size changes occur once per decade, essentially every tool in the factory is changed. This represents an opportunity to have a significant environmental impact because both the manufacturing process and fab must be completely redesigned. Here, step-function type improvements are possible.

Read the complete article in a pdf format.

*Solid State Technology was saddened to hear about the passing of Terry McManus, 58, on January 31. McManus was an Intel Fellow and director of Environmental Health and Safety (EHS) Technologies at Intel’s Technology and Manufacturing Group.

Other February 2005 SST Online Exclusive Features

If you have any questions or comments, please contact:
Julie MacShane, Managing Editor, SST at email: [email protected].


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