May 2006 Exclusive Feature:

Tackling future CMOS challenges outside Moore’s Law

By Bob Haavind, Editorial Director, SST

Is Moore’s Law dead — and if so, does it really matter? That question, posed at a recent SEMI breakfast panel near Boston, brought some surprising answers. Yes, an expert panel agreed, the traditional shrink of Moore’s Law ran into physical limits a few years ago, but it really won’t make that much difference to progress in electronic systems.

While CMOS transistor count/area continues to double every couple of years in accordance with Moore’s Law, performance has hit a ceiling at about 4GHz. The gate insulator can’t be made thinner because of excess leakage, so whole new bag of tricks will be needed to continue the shrink, explained Raj Jammy, head of Sematech’s frontend processes division (on assignment from IBM). Meanwhile, multicore processors, multichip packages, and clever designs are enabling progress in electronic systems capabilities and functionality in spite of the limit on circuit speed.

Jammy discussed the struggle toward 32nm and below, while Fang Xu of Teradyne discussed chip testing challenges. Passive or quiescent power is about to become even greater than active power as device density increases further, so something has to be done to control leakage, Jammy pointed out. High-k dielectrics and metal gates offer a potential solution. High-k materials allow thicker oxides, and metal gates avoid the charge depletion in polysilicon that would cause 50% degradation of inversion thickness compared to only 4% a few years ago when gate dielectrics were thicker. But high-k materials restrict mobility, cutting speed, while metal gates must be tailored to match different energy band edges in p- and n-type transistors, complicating processing.

Sematech is working on ways to integrate tantalum-based metal with hafnium-based high-k dielectrics to meet future gate stack requirements. This approach is preferred to using fully-silicided (FUSI) nickel gates to replace polysilicon because of manufacturing problems, Jammy explained. The FUSI approach causes different stress levels across the wafer due to varying transistor gate lengths, and there are problems in matching n- and p-type band edges, as well as with stability. Nonetheless, many companies and labs are doing extensive work to find solutions to these problems, he added, so eventually FUSI might provide solutions as well.

Strain engineering to increase mobility is being used to maintain or increase circuit speed, and Jammy sees this continuing until the end of the Roadmap, perhaps with some use of germanium or other alternate materials. Doing strain at the wafer level suffers from too many defects, so local stress is used instead. Currently this is uniaxial stress, but biaxial stress may be needed at future nodes.

Traditional rapid thermal processing has gone to spike anneals, which used to be in the few seconds range, but now are done in 5-10 milliseconds to control short channel effects, Jammy said. This is vital as gate lengths narrow.

Transistors may have to go to vertical gates such as FinFETs as the shrink continues, but it is hard to make straight sidewalls on the fins, so Sematech is tackling the problem. Jammy also showed the advantages of using an insulating sublayer, which might move from today’s partially depleted silicon-on-insulator (SOI) to fully depleted in the future.

Jammy and other panelists agreed that even though the traditional scaling of Moore’s Law has run into some physical limits, circuit designers and system architects are finding ways to push performance anyway as they move toward multiprocessing, multithreading, and even massively parallel architectures. Meanwhile, finding ways to integrate high-k dielectrics with metal gates without sacrificing mobility may eventually boost circuit speeds above the 4GHz limit in the future without excessive power dissipation.

Another roadblock faces test system designers, pointed out Feng Xu of Teradyne. According to projections of current trends, by about 2009 it likely will become more costly to test a device than it does to manufacture it, which is unacceptable to chipmakers. Again, help is on the way. Multisite testing allows a few or even many points on the circuitry to be probed concurrently, sometimes doing the same tests in parallel on several devices. If the operating system of the tester can handle highly parallel operations, using extensive background processing to reduce testing time, multisite testing efficiency can be increased dramatically, Xu showed. Attaining this efficiency should not require any extra effort by the user, he added. — B.H.


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