MoSys readies 65nm embedded memory IP

August 7, 2006 – MoSys Inc., a provider of high-density system-on-chip (SoC) embedded memory technology IP, says it has completed the basic R&D phase for porting its 1T-SRAM embedded memory to 65nm semiconductor manufacturing processes.

The company said it has initiated macro design work to move the designs into high-volume consumer SoCs, and signed a license and royalty agreement with a “major” IDM in 2Q. Design work also has begun on 65nm implementations of MoSys’ preconfigured Classic Macro product line with leading pure-play foundries, the company added.

“The density and power advantages of our 1T-SRAM technology continue to improve as we scale to smaller geometries like 65nm,” stated CEO Chet Silvestri.

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