November 17, 2006 – Sarnoff Europe says it has licensed its “TakeCharge” portfolio of on-chip electrostatic discharge protection technology to Fujitsu, for protecting the chipmaker’s 65nm CMOS IC products. The agreement covers a wide range of IC and wafer production, and TakeCharge will be deployed in Fujitsu’s IO libraries as the primary ESD solution for 65nm CMOS.

“More and more major companies [are] struggling to meet industry standard requirements such as 2kV Human Body Model and 200V Machine Model” requirements, noted Koen Verhaege, executive director of Sarnoff Europe. He added that Sarnoff is working to extend the technology to 45nm ESD design.