PACKAGING BEAT: Industry leaders vie for memory-stacking bragging rights

by Jeff Demmin, Contributing Editor, WaferNews

Samsung, Hynix, and Akita Elpida have all made announcements recently about their latest achievements in memory stacking technology. There was definitely a competitive tone to these releases, but they actually appear to be pushing somewhat different agendas.

Akita Elpida was set up less than a year ago by Elpida to develop advanced packaging technology for its DRAM products. The technology includes the chip stacking and package-on-package approaches that many companies are using, and Akita Elpida apparently decided to make a splash by pushing the limits on chip stacking. The result was a stack of 20 chips within the 1.4mm vertical envelope that is a typical target for current DRAM products. Akita’s announcement includes many technical details about their wafer thinning, thin-wafer handling, die handling, low-loop wire bonding, and molding technologies. This served as a reminder that DRAM companies other than the top four have some advanced technology too. Akita admits that all of this technology will be put to use in die stacks up to about seven high for now, so the 20-die stack was used at least in part to get some attention. The technology cited by Akita is evolutionary rather than revolutionary, though, so it should make its way into the mainstream soon.

Hynix also announced the capability to stack 20 chips in a 1.4mm thick package. The Korean memory giant noted that it can thin chips to 25µm, compared to 30µm for Akita Elpida, adding some fuel to the competitive fire. The spin for Hynix is that they are doing it with NAND flash memory chips, which was a way for Hynix to promote itself as something other than a DRAM supplier. A recent NAND flash joint venture announcement with SanDisk also emphasized this point. Diversifying beyond DRAM is one way to mitigate the pricing pressures and cycles faced when a company has been focused on just one type of memory. The exploding market for NAND flash has also made it an appealing target for growth.

Samsung’s stacking technology announcement emphasized their capability as a leader in wafer processing technology, extending that to vertical integration. Specifically, a through-silicon via technology tailored for DRAM was introduced and touted as the first all-DRAM TSV technology. Samsung creates the vias by laser-drilling holes through the wafers and filling them with copper. (Other possible TSV approaches include etching trenches through the silicon.) The introductory DRAM product using the technology is a stack of four 512 Mb DDR2 DRAM, which enables a 4GB DIMM.

Samsung’s announcement of this extension of its TSV technology from NAND flash, which was rolled out a year ago, to DRAM is one indication of integrated device manufacturers (IDMs) taking more control of the vertical integration market. A few years ago, most of the stacking announcements came from packaging sub-contractors, which had their own horse race to see who could stack the most packaged or bare die. But with TSVs moving closer to the mainstream, the IDMs are becoming the leaders — the performance, form factor, and supply chain benefits of TSVs have made it an attractive technology for the top IDMs to have in-house. Samsung’s announcement of DRAM TSVs let the market know that their products will be benefiting from an industry-leading technology. — J.D.

Microscopic views of 20-die multi-chip packages of Samsung Electronics (left) and Hynix (right). By stacking up in tilting steps, Hynix’s package is less susceptible to malfunctions, the company claims. (Source: Korea Times)


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