June 12, 2007 – Tezzaron Semiconductor says it is ramping its 2D “3T-iRAM” line of 72Mbit memory devices at Singapore foundry Chartered Semiconductor on the foundry’s 0.13-micron process technology, and plans to use this SRAM drop-in replacement as the basis for its first 3D ICs. Robert Patti, Tezzaron CTO, discusses both technologies with WaferNEWS.

Instead of a single transistor like a normal DRAM, the “iRAM” uses three transistors, making it very fast and able to be made in a logic process, according to Robert Patti, Tezzaron’s CTO, who discussed the work with Chartered in an interview with WaferNEWS. “It’s a dynamic memory that’s can access data faster than a normal SRAM,” he explained, adding that the speed hides the need to refresh the device. “To the outside user it runs just like a normal SRAM,” and with three transistors instead of six in a normal SRAM makes it slightly less than half the size.

The 3T-iRAM work with Chartered is Tezzaron’s first production of a commercial standalone product, after the technology has been run in other foundries as embedded memory, and Patti said the company will still honor commitments to customers who need the embedded version.

The 3T-iRAM also is designed to store up to 8 bits/memory on an individual cell thanks to a feature called “novel current sensing,” which gauges how much current is put into and drawn from the device, though Patti said that won’t be enabled “for the foreseeable future.”

Meanwhile, Chartered and Tezzaron are also moving ahead to develop 3D-ICs using Tezzaron’s process, with plans to double-stack the 72Mbit devices to create a 144Mbit SRAM “drop-in” replacement. Eventually, they will offer many types of 3D IC memories in two, three, and up to five layers using the TSV technique.

Patti explained Tezzaron’s 3D process as building hundreds of thousands of embedded through-silicon vias dubbed “super contacts” into the circuitry on each wafer (instead of just connecting at the I/O). The wafers are then aligned, bonded, thinned, and diced. By comparison, Samsung’s 3D process uses TSVs at the I/O, meaning ~60 TSVs connecting to I/O pins, but “all the processing is in BEOL” with laser holes, cutting and metal plating, and some kind of solder or wire bonding.

But “if you want lower costs and improved performance, you need to fundamentally redesign the part…not with 10s of TSVs per die, but millions,” he said. Patti claimed that, assuming an “apple-to-apple basis” in which the costs to build wafers are equal, Tezzaron’s stacking “is up to half the cost per bit of a normal 2D process” compared to Samsung.

The 3T-iRAM also is designed to store up to 8 bits/memory on an individual cell thanks to a feature called “novel current sensing,” which gauges how much current is put into and drawn from the device, though Patti said that won’t be enabled “for the foreseeable future.” He acknowledged that the current-sensing feature is a technical roadblock to using voltage-based EDA tools, but pointed out that EDA has always been a problem. “We have to work primarily with SPICE as a simulation tool,” he said, citing long simulation times and cutdown models when dealing with hundreds of millions of transistors.

Patti noted that not a lot has changed about the company’s 3D process in the past 2+ years, including the tools (still using EVG equipment), for which they still have “pretty relaxed alignments.” “We did that intentionally,” Patti said; “one challenge at a time.”

Instead, he said, the key is focusing on minimizing process complexity, and he touted Tezzaron’s comparatively simplistic 3D techniques requiring no new materials or equipment process qualifications vs. other memory firms. The company’s “super contacts” use tungsten, which can be formed at FEOL (using TSV), in what he called a “via first, frontend aligned process.” he added. The bonding involves Cu-to-Cu thermal diffusion, “that’s very well understood.” “To Chartered it doesn’t look special to them at all — just a top layer of copper interconnect without an aluminum pad layer.”

Tezzaron had initially hoped to have the SRAM part in production by the end of 2005, but a variety of delays including a design error requiring an architectural fix and “initial issues getting into foundry” pushed plans out by a year, Patti explained. The company is starting with the higher-performance SRAMs because the technology “allows us to have relatively lax 3D rules” but still build something that cannot be cost-effectively produced in 2D, at prices customers will pay for, and starting with moderate volumes (unlike DRAM).

Tezzaron has been through qualification on 3D DRAM parts which look “very very good,” Patti said, but they’re still accumulating data. He projects to move to early production of DRAMs “sometime next year” — combining controller (logic) wafers from Chartered with other wafers from DRAM foundries in Taiwan — targeting higher-performance DDR2 (up to 1.2GHz) and DDR3 (2.4GHz) ranging from 512Mbit-2Gbit. — J.M.