by John Borland, contributing editor, Solid State Technology
Last week, WaferNEWS reported on research revealed at the recent VLSI Symposium in Japan about high-k dielectrics and metal gates (HK+MG) from top chipmakers including Intel and IBM, as well as NEC, Toshiba, and Samsung. This week WaferNEWS looks at HK+MG work and other leading-edge research being done by consortia, through exclusive interviews with SEMATECH and IMEC.
For the 45nm node, SEMATECH first looked at FUSI, then replacement gates, then finally settled on a gate-first high-k (22-24) metal-inserted poly (MIPS) electrode, according to Byoung Hun Lee, program manager for advanced gate stack (and IBM assignee), in an interview with WaferNEWS. Currently, 50% of the equivalent oxide thickness (EOT) is from the interfacial oxide layer, so this is scalable to 32nm node and it is compatible with high temperature processing, he said. The issues for pMOS can be solved with SiGe channel material for pMOS and MoAlO2 for low-standby power (LSTP) pMOS, as presented in their papers 9A-1 and 9A-4.
Lee sees 45nm and 32nm as straight-forward scaling with no roadblocks, but the 22nm node presents challenges. SEMATECH has a great deal of experience with etching to solve the metal etch problems with HK+MG, though, and he believes the challenges are known, and they simply need to optimize the process. Lee revealed, however, that he is personally concerned that the industry needs to come to a consensus on either gate-first or gate-last, because both approaches cannot be supported.
For frontend processing, SEMATCH is focused on process manufacturing at the 32nm node, stated Raj Jammy, director frontend process (also an IBM assignee). The group’s view is that for scaled devices to be stable, tight control of gate length variation due to lithography and etching will be required, as will control of dopant placement and number of dopant atoms in the channel to prevent fluctuation, assuming no diffusion. The question is whether to control gate length scaling, or use more strain-Si, while also reducing contact resistance. To address these questions, SEMATECH is looking into Ge and SiGe channels for the 32/22nm nodes. For high-k, the consortium’s HfSiON material can go up to a k of 16, and its approach is gate-first because replacement gate scaling is limited. However, Jammy noted that, while addressing HK+MG for nMOS is easy, pMOS presents a problem because of the roll-off of Vfb. He added that for its gate-first approach, SEMATECH has developed a high-k Hf dielectric that can tolerate a 1075°C spike anneal.
SEMATECH has looked at 270 metal gate candidates for high-k metal gate work function tuning, and if the work function starts higher, it rolls off when EOT <2nm. For the 32nm node, the researchers have targeted both HP (high-performance) and LSTP devices; therefore, the issue is how to scale the gate stack. With a replacement gate, the challenge is controlling the sidewall to prevent the keyhole filling problem. Additionally, a high-k dielectric on the vertical sidewall will cause the spacer k value to increase.
Jammy noted that SEMATECH is also working on activities involving FinFET and source/drain doping. The group has made 13nm x 60nm Fins, and wants to achieve a smooth 92° vertical Fin process that is reproducible.
Michael Polcari, SEMATECH president and CEO, told WaferNEWS about other areas that are receiving attention, including a major effort in lithography (EUV and immersion lithography), plus looking at new materials for memory and strain-Si technology, and 3-D wafer/chip bonding.
The area in which SEMATECH is seeing a great deal of interest, Polcari noted, is in its manufacturing program on fab productivity and benchmarking of fabs for optimum high-volume/low-mix, and high-volume/high-mix. To address this topic, they look at their members’ fab equipment and do process equipment matching. Since they changed their model to be more flexible and allow member companies to be a program-based participant, Polcari said that the result has been that new companies have joined the consortia, including NEC, Renesas, Panasonic, TSMC, Samsung, and Micron.
Serge Biesemans, director of CMOS device technology research at IMEC, told WaferNEWS that to meet all the needs of the consortium’s clients, his group is tasked with providing all three high-k gate integration options: 1) gate- and metal-first (MIPS), 2) gate-first and metal last (FUSI), and 3) gate- and metal-last (replacement gate). After four years and 25 papers, IMEC’s FUSI approach is now complete. IMEC had eight papers at the VLSI Symposium out of a total of 86 papers, and all its HK+MG papers were on FUSI — and so work will now focus on developing the other two areas, he noted. Biesemans said the k value for IMEC’s Hf-based oxide is 15 and it can be maintained even with laser annealing processing.
With the MIPS gate-first process, etching two different metals at the same time can be a problem resulting in etch variations. Therefore, gate/metal etch is an issue to maintain precise sidewall profile control and not variation which would increase device variability, Biesemans explained. He added that the gate-last approach avoids the gate metal etch issues. Another issue is with pFET flat band voltage roll-off when the EOT <2.0nm.
At the 45nm node, Biesemans said the majority of companies will still use SiON/poly gate stacks, and then switch to FUSI/high-k at the 32nm node. Moving on to 22nm, his personal view is that because of parasitic capacitance, the industry may need to go into the third dimension by stacking the device, as with multi-core processors. — J.B.
John Borland is founder of J.O.B. Technologies, and a member of SST’s Editorial Advisory Board.