Category Archives: 3D Integration

The Semiconductor Industry Association (SIA) announced worldwide sales of semiconductors reached $29.0 billion for the month of October 2015, 1.9 percent higher than the previous month’s total of $28.4 billion and 2.5 percent lower than the October 2014 total of $29.7 billion. The Americas market posted 3.9 percent growth compared to last month, leading all regions. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects slight market growth for the next three years.

“Global semiconductor sales have shown signs of stabilizing in recent months, with October marking the third straight month of month-to-month growth,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Year-to-date sales are narrowly ahead of where they were through the same time last year, and slight growth is projected for next year and beyond.”

Month-to-month sales increased across all regional markets: the Americas (3.9 percent), China (1.6 percent), Europe (1.2 percent), Japan (0.4 percent), and Asia Pacific/All Other (1.7 percent). Compared to October 2014, sales were up in China (5.7 percent), but down in the Americas (-5.6 percent), Europe (-9.4), Japan (-10.5 percent), and Asia Pacific/All Other (-2.4 percent).

Additionally, SIA endorsed the WSTS Autumn 2015 global semiconductor sales forecast, which projects the industry’s worldwide sales will reach $336.4 billion in 2015, a 0.2 percent increase from the 2014 sales total. WSTS projects year-to-year increases for 2015 in Asia Pacific (3.9 percent), with decreases projected for the Americas (-0.6 percent), Europe (-8.2 percent), and Japan (-10.3 percent).

Beyond 2015, the global market is expected to grow at a modest pace. WSTS forecasts 1.4 percent growth globally for 2016 ($341.0 billion in total sales) and 3.1 percent growth for 2017 ($351.6 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

October 2015

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.82

6.05

3.9%

Europe

2.87

2.90

1.2%

Japan

2.69

2.70

0.4%

China

8.45

8.58

1.6%

Asia Pacific/All Other

8.58

8.72

1.7%

Total

28.41

28.96

1.9%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

6.41

6.05

-5.6%

Europe

3.21

2.90

-9.4%

Japan

3.01

2.70

-10.5%

China

8.12

8.58

5.7%

Asia Pacific/All Other

8.94

8.72

-2.4%

Total

29.68

28.96

-2.5%

Three-Month-Moving Average Sales

Market

May/Jun/Jul

Aug/Sept/Oct

% Change

Americas

5.51

6.05

9.7%

Europe

2.83

2.90

2.5%

Japan

2.63

2.70

2.3%

China

8.18

8.58

5.0%

Asia Pacific/All Other

8.71

8.72

0.2%

Total

27.87

28.96

3.9%

“Advanced packaging will reach 44% of packaging services and a revenue of US$ 30 billion by 2020,” Yole Développement (Yole) announced. Overall, the main advanced packaging market is the mobile sector with end products such as smartphones and tablets. Other high volume applications include servers, PC, game stations, external HDD/USB and more.

According to Yole’s latest advanced packaging report entitled “Status of the Advanced Packaging Industry” (2015 Edition), emerging applications are coming from the IoT world, with wearables and home appliances (connected home) solutions already penetrating the market. Other early stage IoT investments have been also made in smart cities, connected cars, industrial devices, medical applications…

In parallel, the Chinese companies play an important role in the advanced packaging market growth: “At Yole, we see an increased activity of Chinese capital in the advanced packaging industry,” explains Andrej Ivankovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole. “The objective of the semiconductor transformation in China is to decrease external dependency and set up a complete internal supply chain that can serve domestic and international customers.”

In this context, what would be the evolution of the advanced packaging industry? What will be the status of the supply chain by 2020? Which packaging technologies will be the most critical tomorrow and after? With the emergence of IoT applications, the development of local Chinese industry and numerous M&A coming from the overall semiconductor industry and the direct impact on the advanced packaging supply chain. Yole’s advanced packaging analysts offer you insight into the new advanced packaging world.

“Status of the Advanced Packaging Industry” report (2015 edition) released by Yole, the “More than Moore” market research and strategy consulting company, provides an high added-value market overview of the industrial landscape; under this new report, Yole’s advanced packaging team proposes a comprehensive analysis of the technology trends and also assesses the future development of the advanced packaging market.

packaging industry graph

This analysis confirms the market positioning of Yole and highlights the knowledge and deep understanding of the company within this industrial field.

According to Yole’s estimates, advanced packaging services revenue will increase by US$9.8 billion from 2014 to 2020 at a CAGR of 7%, in majority due to high volume adoption of Fan-Out WLP, 2.5D/3D and evolution and growth of Fan-In WLP and flip-chip. Advanced packages currently account for 38% of all packaging services or US$ 20.2 billion and are expected to grow share to 44% and US$ 30 billion by 2020.

The mobile sector remains the main advanced packaging market with smartphones and tablets as end products. Other high volume applications include servers, PC, game stations, HDD/USB, WiFi hardware, base stations, TVs and set top boxes. The scent of IoT is spreading with first products already on the market in the form of wearables and smart home appliances. Further early stage investments are made in sectors such as smart cities, connected cars, various industrial devices and medical applications.

The flip-chip platform represents a large mature market and leads in packaging services revenue and wafer count. Fan-In WLP leads in unit count due to small size compared to demanded volume. Adoption of wafer level packages continues. Teardowns performed by Yole and its sister company, System Plus Consulting on 3 high end smartphones (more info on i-micronews.com, reports section or click here directly for iPhone 6+, Samsung Galaxy S6 as well as the Huawei Ascend Mate 7 analysis, that will be available soon) indicated a high penetration rate of WLP, 30% on average. Fan-Out WLP is expected to make a major breakthrough within the next year, likely led by TSMC inFO PoP and followed by other Fan-Out multi die solutions. Long term, a bright future lies ahead for wafer level packages with respect to IoT requirements as they are well position to answer related cost, form and functional integration demands. When it comes to advanced feature sizes, a competitive sub 10 µm / 10 µm arena is established where organic wafer level packages aggressively compete with advanced organic flip-chip substrates and 2.5D / 3D Si/glass interposers.

As WLP pin counts grow, thicknesses and overall cost decrease, the evolution of Fan-In WLP and in particular a breakthrough of Fan-Out WLP are expected to result in a takeover of a part of the flip-chip market. With the breakthrough of Fan-Out WLP, the packaging landscape might drastically change, with an IDM and foundry leading all packaging services by wafer count.

The full advanced packaging analysis is today available; in the report Yole’s analysts present revenue, wafer and unit forecasts per advanced packaging platform and production breakdown by device type such as analog/mixed signal, wireless/RF, logic and memory, CMOS image sensors, MEMS, LED and LCD display drivers.

Intel and ASM look to TCB


November 17, 2015

BY PHIL GARROU, Contributing Editor

In the September column, we looked at some of the key thermo-compression bonding (TCB) papers at ECTC. Is there any question that TCB is real and will be the next big bonding technology? The focus this month is more on this very important new assembly process from Intel and ASM.

Intel introduced TCB into high volume manufacturing in 2014. As substrate and die become thinner and solder bump sizes and pitches get smaller, the thin organic substrate tends to warp at room temp and as the temp is increased during the reflow process. The thin die can also demonstrate temperature dependent warpage, which can come into play during the reflow process. The extent of warpage of the substrate and die at high temperatures can overcome the natural solder surface tension force leading to die misalignment with respect to the substrate, resulting in tilt, non-contact opens (NCO) and in some cases solder ball bridging (SBB). FIGURE 1 shows these various defects.

Phil Garrou

In the Intel TCB process, the substrate with pre-applied flux is held flat on the hot pedestal under vacuum. The die is picked up by the bond head, held securely and flat on the bond head with vacuum. After the die is aligned with the substrate, the bond head comes down and stops when the die touches the substrate. A constant force is then applied while the die is heated up quickly beyond the solidus temperature. As soon as the solder joint melts, the die is moved further down (solder chase) to ensure all solder joints are in contact. The die is held in position allowing the solder to reflow completely, and to wet the bump pads and copper pillars. While the solder is still in the molten state, the bond head retracts upwards controlling the solder joint height. The bond head then releases the vacuum holding the die and moves away as the solder joints have solidified. The major process parameters, i.e temperature, force and displacement are continuously monitored during the TCB bonding process.

Large differences in the CTE between the organic substrate and die results in different magnitude of expansions when heated which can lead to serious bump offset at corners. To minimize the thermal expansion mismatch, the substrate is processed at a lower temperature (e.g. 140°C) while the die and solder is rapidly heated up for reflow and cooled down for solidification using a pulse heater with heating ramp rate exceeding 100°C/s and cooling ramp rate exceeding 50°C/s. This reduces the heat transfer to the substrate. The bulk of the substrate can remain at low temperature and does not expand extensively.

In another ASM paper on TCB they examined what they call liquid phase contact (LPC) TCB. The goal is to increase the throughput of the TCB process. Process flow is shown below. Flux is printed or sprayed on the substrate. Then the bonding head picks up a die from the carrier at an elevated temperature, but below the solder melting point. Then the bonding head is heated up to a temperature higher than the solder melting point and the chip is aligned with the substrate. The chip is then contacted and wetted on the substrate at a predeter- mined bonding height. After a predetermined bonding time, the bonding head can move is cooled down to a temperature below the melting point of solder. They claim this results in attachment of 1200 units/hr vs 600 for the standard TCB flux process.

Researchers from RMIT University in Melbourne have helped crack the code to ultra-secure telecommunications of the future in an international research project that could also expedite the advent of quantum computing.

A team co-led by RMIT MicroNano Research Facility Director Professor David Moss has added a new twist to create photon pairs that fit on a tiny computer chip.

Researchers pioneered a new approach to create photon pairs that fit on a computer chip. Credit: RMIT University

The breakthrough, published in Nature Communications, heralds the next-generation of integrated quantum optical technology, being compatible with current technology and secure communications.

The team pioneered a new approach based on a micro-ring resonator – a tiny optical cavity – in which energy conservation constraints can be exploited to suppress classical effects while amplifying quantum processes.

They used laser beams at different wavelengths and then had to overcome the risk of the two pump beams being able to destroy the photons’ fragile quantum state.

“One of the properties of light exploited within quantum optics is ‘photon polarization’, which is essentially the direction in which the electric field associated with the photon oscillates,” Moss said.

“Processes used to generate single photons or photon pairs on a chip allow the generation of photons with the same polarization as the laser beam, forcing us to find a way to directly mix, or cross-polarize, the photons via a nonlinear optical process on a chip for the first time.”

Moss worked with Professor Roberto Morandotti at the INRS-EMT in Canada and researchers from the University of Sussex and Herriot Watt University, City University of Hong Kong, and the Xi’an Institute in Chin, on the research.

“While a similar suppression of classical effects has been observed in gas vapours and complex micro-structured fibres, this is the first time it has been reported on a chip, opening a route for building scalable integrated devices that exploit the mixing of polarization on a single photon level,” he said.

“It also has the advantage that the fabrication process of the chip is compatible with that currently used for electronic chips which not only allows the exploitation of the huge global infrastructure of CMOS foundries, but will ultimately offer the potential to integrate electronic devices on the same chip.

“Both of these are fundamental requirements for the ultimate widespread adoption of optical quantum technologies.”

SAN JOSE, Calif. — Nov. 11, 2015 — Ultratech, Inc., a supplier of lithography, laser-processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HB-LEDs), as well as atomic layer deposition (ALD) systems, today introduced the Superfast 4G+  in-line, 3D topography inspection system. Ultratech’s new 4G+ system builds on the field leadership of the Superfast 4G, providing the industry’s highest-productivity and lowest-cost solution for high-volume manufacturing. The Superfast 4G+ system’s patented coherent gradient sensing (CGS) technology enables Ultratech customers to use a single type of wafer inspection tool to measure patterned wafers across the entire fab line at the lowest cost. Ultratech plans to begin shipping the Superfast 4G+ systems in the first quarter of 2016.

Superfast 4G+ features include:

  • Direct, front-side 3D topography measurement for opaque and transparent stacks patterned wafers
  • 150 wph, the highest industry 3D in-line inspection throughput with the smallest footprint
  • 1-mm edge exclusion enabling full-wafer pattern inspection and thin-film 3D process control
  • Large bow option for in-line manufacturing control of highly bowed wafers without impacting throughput

Damon Tsai, Ultratech Asia Director for Inspection Systems, said, “Our current leadership position in in-line 3D inspection at advanced memory and foundry manufacturers with Superfast 4G has provided us with a tremendous learning environment. Our partners have helped us develop new hardware capabilities like the ‘Recipe Driven Range Control,’ an innovative high-throughput, large bow optical option on board the Superfast 4G+, as well as new fleet management performance metrics. The inherently simple design of the CGS technology is enabling us to rapidly deliver new capabilities and performance improvements over more complex optical solutions.”

Based on patented CGS technology, Ultratech’s Superfast 4G+ inspection system provides the industry’s highest throughput (150 wph) with the lowest cost-of-ownership compared to competing systems. The direct, front-side 3D topography measurement capability is well-suited for patterned wafer applications such as lithography feed-forward overlay distortion and edge-defocus control as well as thin-film deposition stress and planarization control. Delivering a 2X improvement in performance with fleet matching TMU (Total Measurement Uncertainty), along with the ability to measure opaque and transparent stacks on patterned wafers, the Superfast 4G+  provides cost-effective technology to address the critical needs of its global customers. In addition, leveraging the same breakthrough CGS optical module, the Superfast 4G+ is available as a field upgrade of the Superfast 4G.

11/3/2015 Update: The deadline for papers has been extended to November 11, 2015

SEMI announced today that the deadline for presenters to submit an abstract for the 27th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is November 2. ASMC, which takes place May 16-19, 2016 in Saratoga Springs, New York, will feature technical presentations of more than 90+ peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, as well as educational tutorials.

ASMC continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts. Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. Technical abstracts are due November 2, 2015. 

This year SEMI is including two new technology areas: 3D/TSV/Interposer and Fabless Experience. SEMI is soliciting technical abstracts in these key technology areas:

  • 3D/TSV/Interposer
  • Advanced Metrology
  • Advanced Equipment Processes and Materials
  • Advanced Patterning / Design for Manufacturability
  • Advanced Process Control (APC)
  • Contamination Free Manufacturing (CFM)
  • Data Management and Data Mining Tools
  • Defect Inspection and Reduction
  • Discrete Power Devices
  • Enabling Technologies and Innovative Devices
  • Equipment Reliability and Productivity Enhancements
  • Fabless Experience
  • Factory Automation
  • Green Factory
  • Industrial Engineering
  • Lean Manufacturing
  • Yield Methodologies

Complete descriptions of each topic and author kit can be accessed at http://www.semi.org/en/node/38316. If you would like to learn more about the conference and the selection process, please contact Margaret Kindling at [email protected] or call 1.202.393.5552.   

Papers co-authored between device manufacturers, equipment or materials suppliers, and/or academic institutions that demonstrate innovative, practical solutions for advancing semiconductor manufacturing are highly encouraged. To submit an abstract, visit http://semi.omnicms.com/semi/asmc2016/collection.cgi

Technical abstracts are due November 2, 2015. To learn more about the SEMI Advanced Semiconductor Manufacturing Conference, visit http://www.semi.org/asmc2016.

San Jose, Calif., October 29, 2015 — Ziptronix, Inc., a wholly owned subsidiary of Tessera Technologies, Inc. and a leader in low temperature wafer bonding technology, today announced it has entered into a development agreement with Fraunhofer IZM-ASSID. The companies will work together to integrate Ziptronix Direct Bond Interconnect (DBI®) technology into Fraunhofer’s state of the art 300mm wafer production line and demonstrate DBI as the industry’s finest pitch, thinnest and lowest total cost-of-ownership 3D integration solution.

Increasingly, the industry is looking toward 2.5D and 3D-IC solutions as the most cost effective and efficient means of delivering the next generation of high performance computing and consumer electronic products. However, conventional approaches rely heavily on thru silicon vias (TSVs), micro-bumping and underfill, which can limit interconnect density, performance, form factor and cost-effectiveness. Ziptronix DBI technology can address these limitations and accelerate the adoption of game-changing 2.5D and 3D-IC architectures.

“Although great progress has been made, the industry continues to face challenges associated with the manufacturability, scalability and cost of current 2.5D and 3D-IC solutions. Ziptronix’s DBI technology is an enabling platform that can readily address many of these challenges,” said Juergen Wolf, Head of Fraunhofer IZM-ASSID. “We at Fraunhofer are very excited to work with Ziptronix to demonstrate the benefits of DBI technology to our customers on our 300mm wafer production line.”

“DBI is the industry’s highest density, highest performance, lowest profile and lowest cost-of-ownership 3D integration platform,” said Paul Enquist, Vice President of 3D R&D at Ziptronix. “It will revolutionize the world’s most challenging 3D-IC structures and devices, and we look forward to working closely with Fraunhofer to demonstrate this enabling capability to customers around the world.”

“The acquisition of Ziptronix, and the subsequent integration of its team and technology into Tessera, has allowed us to significantly expand the 2.5D and 3D value that we bring to our customers, and the response has been incredibly positive,” said Craig Mitchell, President of Invensas. “This development agreement with Fraunhofer is an important step in the continuing development of the DBI technology as we grow our 2.5D and 3D product offerings.”

Caen, Oct. 22, 2015 – Two years after the launch of the PICS project (funded by the FP7 funding instrument dedicated to research for the benefit of SMEs), three European SMEs, IPDiA, Picosun, and SENTECH Instruments along with CEA-Leti and Fraunhofer IPMS-CNT announce the major technological results achieved during this program.

Started in September 2013, the PICS project was focused on developing innovative dielectric materials deposited by atomic layer deposition (ALD) and related tools (ALD batch tool and etching tool) to bring to mass production a new technology of high- density and high-voltage 3D trench capacitors targeting high-end markets like medical or aeronautics. Capacitors are key components presented in every electronic module. The integrated silicon capacitors technology offered by the SME IPDiA outperforms current technologies (using ceramic or tantalum substrates) in stability in temperature, voltage, aging and reliability and enables to build highly integrated and high-performance electronic modules.

The consortium’s three major technological results are:

  • A novel ALD batch tool was developed by Picosun and Fraunhofer IPMS-CNT. It enables to reduce cost-of-ownership and deliver better uniformity and step coverage for high-K dielectrics into 3D structures. With its demonstrated, optimized, and production-proven ALD processes, Picosun is solidifying its position as a technological leader in the IC, Semiconductor, MEMS markets, from R&D to production systems.
  • A new process for accurately etching high-K dielectrics, which are very specific materials, was demonstrated by SENTECH with the help of Fraunhofer IPMS-CNT. As a result, SENTECH has the potential to gain market share in the field of high-k materials, which have high interest for different applications, e.g. LED, MEMS, magnetic data storage.
  • Two new dielectric stacks were developed and integrated into the IPDiA 3D trench capacitors by IPDiA, CEA-Leti and Fraunhofer IPMS-CNT. The initial specifications were fulfilled and proven by electrical measurements. A new record on capacitance density (>500nF/mm² at 3.3V) and an extended operation voltage (10V with 150nF/mm²) were obtained, which expands IPDiA’s ability to meet current market requirements particularly in the field of medical or aeronautics. Qualification procedure was initiated during the project by launching preliminary reliability studies and it will continue in the coming months.

On top of these R&D results, the other main objective of PICS was the industrialization of this new integrated capacitors technology. Thanks to the partnerships set up, the manufacturability and financial viabilities were ensured by developing adequate industrial tools targeting mass production.

The PICS project is a success for all three SMEs and a good example of the benefits brought by the EU funding instrument “Research for the benefit of SMEs”. The SMEs were able to outsource a part of their research to get from RTD performers innovative know-how and cutting-edge technological processes. The project was built to answer the SMEs’ specific needs and a common goal was set up around the new IPDiA capacitors technology and the specific tools (ALD batch tool and etching) required for its commercial exploitation.

 

Lam Research Corporation (LRCX) and KLA-Tencor Corporation (KLAC) today announced that they have entered into a definitive agreement for Lam Research to acquire all outstanding KLA-Tencor shares in a cash and stock transaction. The move, unanimously approved by the boards of directors of both companies, will create a combined company with approximately $8.7 billion in pro forma annual revenue.

The combined company expects to realize $250 million in cost savings within 18 to 24 months of closing, and anticipates gaining approximately $600 million in incremental revenue by 2020 through improved differentiation of each company’s products and creation of new capabilities.

“This is just what the doctor ordered,” Srini Sundararajan, Semiconductor and Semicaps Analyst for W.R. Hambrecht + Co./Summit Research, wrote in an analysis of the move. “It removes excessive dependence of LRCX on memory and excessive dependence of KLAC on foundry/logic.”

According to the LRCX press release, “the combination will create unmatched capability in process and process control, delivering optimized results in partnership with its customers by reducing variability and accelerating yield, ultimately helping the semiconductor industry extend Moore’s Law and performance scaling generally.”

“The pairing of Lam Research and KLA-Tencor brings industry leadership in process and process control together, accelerating our capability to address our customers’ most difficult challenges as they scale to meet the market demands of lower power, higher performance, and smaller form factors,” said Martin Anstice, Lam’s president and chief executive officer. “Lam Research and KLA-Tencor’s shared commitment to collaboration and building strong customer trust, along with our respective track records of innovation, product leadership, and operational excellence, position us as a combined company to deliver the higher levels of technology differentiation and speed to solutions that are critical to our customers’ long-term success.”

“I strongly believe that this transaction represents a great outcome for all of KLA-Tencor’s key stakeholders,” said Rick Wallace, president and chief executive officer of KLA-Tencor. “The combined company will be uniquely positioned to work collaboratively with our customers to help them meet the challenges of FinFET, multi-patterning and 3D NAND development.  Given the complementary nature of the two companies’ product offerings and technologies as well as the lack of product overlap, the combination will create an industry leader with greater opportunities for our respective employees for professional development and growth. Lastly, this transaction will benefit our stockholders who will receive compelling upfront value, in addition to the opportunity to own a meaningful stake in an industry leader and participate in the upside potential created by the combination.”

According to the press release, the transaction is expected to close in mid-calendar year 2016, pending customary regulatory approvals. The transaction is also subject to customary closing conditions, including the adoption by KLA-Tencor’s stockholders of the merger agreement and the approval by Lam Research’s stockholders of the issuance of shares in the transaction. Given their complementary product lines and the industry benefits the transaction will enable, the companies believe that they will be able to obtain the requisite regulatory approvals on a timely basis.

Analyst Sundararajan agrees: “We expect minimal opposition to this deal from the various jurisdictions, rather easily handled.”

However, Robert Maire of Semiconductor Advisors thinks approval could potentially be more difficult. “We think this is going to be the obvious biggest issue after the failed AMAT & TEL merger.  We think there will likely be opposition in the semi industry but probably less so than we heard the screaming related to AMAT/TEL,” he wrote. “While maybe not overjoyed, the combination makes a lot of sense for customers and feels a lot less negative than the failed AMAT/TEL.”

According to the press release, some of the benefits the combined company expects to see are:

  • Creates Premier Semiconductor Capital Equipment Company: Strengthened platform for continued outperformance, combining Lam’s best-in-class capabilities in deposition, etch, and clean with KLA-Tencor’s leadership in inspection and metrology
  • Accelerated Innovation: Increased opportunity and capability to address customers’ escalating technical and economic challenges
  • Broadened Market Relevance: Comprehensive and complementary presence across market segments provides diversity, scale and value creating innovation opportunities
  • Significant Cost and Revenue Synergies: Approximately $250 million in expected annual on-going pre-tax cost synergies within 18-24 months of closing the transaction, and $600 million in annual revenue synergies by 2020
  • Accretive Transaction: Increased non-GAAP EPS and free cash flow per share during the first 12 months post-closing
  • Strong Cash Flow: Complementary memory and logic customer base, operational strength, and meaningful installed base revenues strengthen cash generation capability

According to Sundararajan, the move could have negative impacts for some other companies in the industry. “This deal is quite negative for Applied Materials (AMAT) and Hermes Microvision and perhaps for ASML also,” he wrote. “In the case of AMAT, their process diagnostics and control division being based in Israel does not allow of meshing of capabilities, and product synergies really don’t exist.  In the case of Hermes Microvision, since etch is the pre-dominant user of e-beam inspection due to testing of contacts, a combination of KLAC and LRCX with both e-beam and etch capabilities can be lethal.”

Maire also foresees difficulties for competitors: “The combined LAM and KLA creates a powerhouse in the semicap industry, which is looking a lot more like a duopoly.”

Lam president and CEO Anstice concluded, “We have tremendous respect for the company KLA-Tencor employees have built over nearly 40 years — their culture, technology, and operating practices. I have no doubt that our combined values, focus on the customer, and complementary technologies will create a trusted leader in our industry, capable of creating significant opportunity for profitable growth and in turn delivering tremendous value to all of our stakeholders. This is the right time for the right combination in our industry.”

Entegris, Inc., a producer of yield-enhancing materials and solutions for highly advanced manufacturing environments, has expanded its wafer shipper family of products with the SmartStack (R) 300 mm Contactless Horizontal Wafer Shipper (HWS). The SmartStack 300 mm is the industry’s first contactless horizontal wafer shipper capable of holding a full lot of 25 wafers, almost twice the capacity of competitive wafer shippers. Entegris’ design departs from traditional interleaf inserts and foam cushions by using a perimeter support ring to contain wafers inside. The wafers are positioned so that they move in unison, preventing wafer-to-wafer contact and potential damage from impact.

“We designed an ideal solution for shipping and storing 25-lens bumped or thin wafers that offers improved safety over conventional wafer shippers,” said Entegris Product Marketing Manager, Doug Moser. “By placing the wafers on rings and removing the interleaf inserts and foam cushions, the wafers are protected from stains, imprints and scratches typically caused by these inserts. Additionally, the new design accommodates 25 wafers in one shipper, thereby increasing shipping density and lowering shipping cost 50% or more, compared with a conventional FOSB.”

The SmartStack 300 mm is designed to accommodate wafers of varied thickness (150 µm to 1100 µm), for a variety of applications including 3D, 2.5D, SoC, MEMS, LED and power semiconductors. The new design is also available in the 150 mm and 200 mm size. The automation-compatible features of the 300 mm HWS enable ease-of-use and limit manual intervention.