Category Archives: 3D Integration

IEEE S3S 2015 could be the turning point for monolithic 3D. From October 4-7 we will have the option to get a short course, invited and selected presentations from a broad range of the industry representatives. They include major vendors such as Qualcomm, Global Foundries, and Applied Materials; leading research organization like CEA Leti, Taiwan National Applied Research Labs, German IMS Chips, and NASA; leading Universities like Berkeley and Stanford; and start-ups like SiGen and MonolithIC 3D.

In its tutorial session, Qualcomm will explain why it is investing in and promoting 3D VLSI (3DV) as an alternative scaling technology, as is illustrated by the following two slides:

GameChang2-0_Fig1GameChange2-0_Fig2

Yet many people still have doubts, as reflected by the title of the panel we were invited to participate in — “Monolithic 3D: Will it Happen and if so…” — at the IEEE 3D-Test Workshop on October 9, 2015.

The doubts likely relate to the technology challenge that is illustrated in the following slide:

GameChange2-0_Fig3

The question, in short, is how we can add more transistors monolithically interconnected to the underlying transistors without exceeding the thermal budget for the underlying transistors and interconnect.

The current paths to monolithic 3D involve major changes to the front line process flow and require the development of a new logic transistors. The big concern is that leading edge vendors are too busy with dimensional scaling and if anything else could be done it seems that FD-SOI would be it, while trailing edge fabs are, in most cases, avoiding any major transistor process development. The recent failure of Suvolta could be an indication of this reality.

Hence the importance of Game-Changing 2.0, a major technology innovation to be unveiled on Wednesday by MonolithIC 3D in a paper titled: “Modified ELTRAN (R) – A Game Changer for Monolithic 3D”. The paper will present a novel use of the ELTRAN process developed by Canon about 20 years ago, primarily for SOI applications. Using ELTRAN (Epi. Layer Transfer) techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change its current front-line fab process. This flow is further simplified and could be integrated with the monolithic 3D flow introduced last year that leverages the emerging precision bonders, such as EVG’s Gemini (R) XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge to its adopters. In addition, this game-changing breakthrough offers a very cost-competitive flow. The following chart illustrates the original use of ELTRAN process for the fabrication of SOI wafers:

GameChange2-0_Fig4

In the “Invited Talks on M3DI” at the conference we will have an opportunity to learn from the inventor of the ELTRAN process, Dr. Takao Yonehara, currently with Applied Materials, in his “Epitaxial Layer Transfer Technology and Application” talk. Prior to Applied Materials, Dr. Yonehara worked with Solexel, a Silicon Valley startup, to deploy the ELTRAN process for low cost solar cell fabrication. Yonehara’s talk will be followed by Prof. Joachin Burghartz of Institute for Microelectronics in Stuttgart, discussing “Ultra-thin Chips for Flexible Electronics and 3D ICs” that uses a variation of such flow in small scale production.

The semiconductor industry is bifurcating these days into a segment that follows aggressive scaling for few super-value applications supported by very few vendors, while the bulk of the industry is enhancing old fabs targeting mainstream applications and the emerging IoT opportunities. Further enhancing these older fabs with monolithic 3D offers a most effective return on investment. Game-Changing 2.0 means that without a need for major process R&D efforts or new equipment, the path for 3D scaling is now open with enormous advantages for IoT. Accordingly, my answer to the original question above is summarized by the title of our invited talk at the IEEE 3D-Test Workshop: “Monolithic 3D is Already Here — the 3D NAND — and Now it would be Easy to Adapt it for Logic.”

In addition the other division, SOI and SubVt provide good complementing technology updates for the power-performance objectives that are so important for these emerging markets.

So, come to the S3S and enjoy unique key technologies update with the great wine and country pleasures of Sonoma Valley.

Novati Technologies Inc., a global nanotechnology development center, today announced the availability of the industry’s most advanced Integrated Sensor Platform, placing a wide variety of sensors onto multi-layer stacks of wafers in order to consume less power and perform significantly faster while reducing overall footprint. Already proven for customer devices at Novati’s commercial development and manufacturing center, the platform paves the way for stacking single or multiple sensors with a broad selection of popular–as well as emerging–substrate materials, enabling new high-end applications for markets that include medical, semiconductors, photonics, security, and aerospace.

Demonstrating a version of this capability for high-performance computing, Novati last month jointly announced with Tezzaron Semiconductor the industry’s first eight-layer 3D IC wafer stack containing active logic, which controls the memory layers. The transistor and interconnect densities per cubic millimeter were far higher than achievable with 2D 14nm silicon fabrication, representing the densest 3D IC ever reported. Not limited to the high-end markets served by that achievement, Novati’s Integrated Sensor Platform also offers great promise as an enabler for the Internet of Things (IoT).

“Energy harvesting is one of the important capabilities needed for the broad set of markets that aim to utilize the integration of sensing and processing,” said Tony Massimini, Chief of Technology for Semico Research. “Novati’s platform offers technology for integrating this energy harvesting ecosystem that includes energy generator, converters, power management, MCUs, energy storage and connectivity for small, wireless autonomous devices, like those used in wearable electronics and wireless sensor networks.”

For the past three years, Novati has demonstrated wafer-to-wafer integration of up to eight wafers, as well as custom sensors integrated directly onto mainstream CMOS architectures. With 3D manufacturing options available on both 200mm and 300mm lines, Novati offers circuit designers an unprecedented degree of freedom to architect the smart sensors of the future.

“While the ability to create multi-chip devices has been around for decades, Novati’s innovative sensor platform can accelerate the Internet of Things by expanding the ways for devices to connect and interact with all types of environments,” said David Anderson, President and CEO of Novati. “Using this platform, the world can integrate novel sensor functionality to virtually any circuitry, including digital logic, analog, mixed signal and memory–and stacking multiple sensors will soon follow. This opens a new, unlimited landscape for designers to significantly improve functionality while reducing costs and time to market.”

As an example of Novati’s substrate integration, their nanomanufacturing site bonded Tezzaron’s wafers directly, wafer-to-wafer, producing devices that can be thinned and finished to the same thickness as conventional 2D dies. The result was excellent electrical, thermal and mechanical performance. Novati’s capability to integrate sensors with such a stacked platform already has led to novel, proprietary product development for several customers.

Building on its ability to provide the world’s most advanced Integrated Sensor Platform and other innovations for the microelectronics markets, Novati intends to open its next office in Europe, where site selection is underway. In order to jointly plan new devices using novel materials that enable micro- and nanoscale functions and analyses, the company will be meeting with companies from around the globe during its participation at SEMICON Europa electronics conference in Dresden for the week of October 6.

“Europe has always been an important market for us and we are excited to continue expansion in this area,” said Julian Searle, Director of Account Management for Novati. “As the innovation initiatives in Europe continue to progress, Novati’s commercialization services and solutions are often the first call for technical pioneers that need to transform great ideas into great products.”

When the world’s leading scientists and engineers in micro/nanoelectronics convene in Washington, D.C. this December for the 61st annual IEEE International Electron Devices Meeting (IEDM), the subjects under discussion will encompass a range of topics critical to the continuing progress of the industry:

  • how to make transistors that are vanishingly small
  • a growing emphasis on low-power devices for mobile & Internet of Things (IoT)
  • alternatives to silicon transistors
  • 3D IC technology
  • a broad range of papers that address some of the fastest-growing specialized areas in micro/nanoelectronics, including silicon photonics, physically flexible circuits and brain-inspired computing.

The 2015 IEDM will take place at the Washington D.C. Hilton Hotel from December 7-9, 2015, preceded by day-long short courses on Sunday, Dec. 6 and a program of 90-minute tutorials on Saturday, Dec. 5. In addition to a technical program of some 220 papers, other events will take place during the meeting, including evening panels, special focus sessions, IEEE awards, and an entrepreneurial luncheon sponsored by IEDM and IEEE Women in Engineering.

Back for the third year, the 2015 IEDM will feature a slate of designated focus sessions on topics of special interest. This year’s topics are:

  • Neural-Inspired Architectures: From Ultra-Low Power Devices To Applications
  • 2D Layered Materials And Applications
  • Power Devices And Their Reliability On Non-Native Substrates
  • Flexible Hybrid Electronics
  • Silicon-Based Nano-Devices For Detection Of Biomolecules And Cell Functions

“From its inaugural meeting until today, the IEDM conference has been the place where breakthroughs that drive the electronics industry forward are unveiled,” said Mariko Takayanagi, IEDM 2015 Publicity Chair and Senior Manager at Toshiba. “For example, at the IEDM in 1975 Intel’s Gordon Moore gave a talk that refined his earlier prediction of transistor scaling into what has since become known as Moore’s Law. That tradition of attracting the best speakers and a large, diverse audience from around the world continues, with a focus this year on devices intended to support the Internet of Things and other emerging areas of importance that depend upon advances in semiconductor technology.”

The official Call for Papers has been issued for the 2016 Symposia on VLSI Technology and Circuits, to be held at the Hilton Hawaiian Village June 13-16, 2016 (Technology) and June 15-17, 2016 (Circuits). The deadline for paper submissions to both conferences is January 25, 2016. The late-news paper submissions deadline for the Symposia on VLSI Technology is March 24, 2016; there is no late-news submission for the Symposium on VLSI Circuits. Complete details for paper submission can be found online at: http://www.vlsisymposium.org/authors/

For the past 28 years, the combined annual Symposia on VLSI Technology and Circuits has provided an opportunity for the world’s top device technologists, circuit and system designers to engage in an open exchange of leading edge ideas at the world’s premier mid-year conference for microelectronics technology. Held together since 1987, the Symposia on VLSI Technology and Circuits have alternated each year between sites in the US and Japan, enabling attendees to learn about new directions in the development of VLSI technology & circuit design through the industry’s leading research and development presentations.

The comprehensive technical programs at the two Symposia are augmented with short courses, invited speakers and several evening panel sessions. Since 2012, the Symposia have presented joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees.

The Symposium on VLSI Technology seeks technical innovation and advances in all aspects of IC technology, as well as the emerging IoT (Internet of Things) field, including:

  • IoT systems & technologies, including ultra-low power, heterogeneous integration, sensors, connectivity, power management, digital/analog, microcontrollers and application processors
  • Stand-alone & embedded memories, including DRAM, SRAM, non-volatile and emerging memory technologies
  • CMOS Technology, microprocessors & SoCs, including scaling, VLSI manufacturing concepts and yield optimization
  • RF / analog  /digital technologies for mixed-signal SoC, RF front end; analog, mixed-signal I/O, high voltage, imaging, MEMS, integrated sensors
  • Process & material technologies, including advanced transistor process and architecture, modeling and reliability; alternate channel; advanced lithography, high-density patterning; SOI and III-V technologies, photonics, local interconnects and Cu/optical interconnect scaling
  • Packaging technologies & System-in-Package (SiP)
  • Photonics Technology & “Beyond CMOS” devices 

The Symposium on VLSI Circuits seeks original papers showcasing technical innovations and advances in the following areas:

  • Digital circuits and processor techniques for standalone and embedded processors
  • Memory circuits, architectures & interfaces for volatile and non-volatile memories, including emerging memory technologies
  • Clock generation and distribution for high-frequency digital and mixed-signal applications
  • Analog and mixed-signal circuits, including amplifiers, filters and data converters
  • Wireline receivers & transmitters, including circuits for inter-chip and long-reach applications
  • Wireless receivers & transmitters, including circuits for WAN, LAN, PAN, BAN, inter-chip and mm-wave applications
  • Power management circuits, including battery management circuits, voltage regulators, energy harvesting circuits
  • Application-oriented circuits & VLSI systems, imagers, displays, and sensors for biomedical and healthcare applications

Joint technology and circuits focus sessions feature invited and contributed papers highlighting innovations and advances in materials, processes, devices, integration, reliability and modeling in the areas of advanced memories, 3D integration, and the impact of technology scaling on advanced circuit design. Submissions are strongly encouraged in the following areas of joint interest:

  • Design in scaled technologies: scaling of digital, memory, analog and mixed-signal circuits in advanced CMOS processes
  • Design enablement: design for manufacturing, process/design co-optimization, on-die monitoring of variability and reliability
  • Embedded memory technology & design: SRAM, DRAM, Flash, PCRAM, RRAM, MRAM and NVRAM memory technologies
  • 3D & heterogeneous integration: power and thermal management; inter-chip communications, SIP architectures and systems

Papers sought for “big integration”

Authors are encouraged to submit papers that showcase innovations that extend beyond single ICs and into the module, including focus areas in the Internet of Things (IoT), industrial electronics, “big data” management, biomedical applications, robotics and smart cars. These topics will be featured in focus sessions as part of the program.

Best Student Paper Award

Awards for best student paper at each Symposia will be chosen, based on the quality of the papers and presentations. The recipients will receive a financial award, travel cost support and a certificate at the opening session of the 2017 Symposium. For a paper to be reviewed for this award, the author must be enrolled as a full-time student at the time of submission, must be the lead author and presenter of the paper, and must indicate on the web submission form that the paper is a student paper.

By Zvi Or-Bach, Contributor

The upcoming IEEE S3S Conference 2015 in Sonoma, CA, on October 5-8, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those that drive the high-volume PC and smart-phone market. The Gartner slide below illustrates this industry bifurcation where traditional mass products follow the ever more expensive scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek a place near its minimum.

S3S_Gartner

The current high-volume market is focused on a few foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs and a broad range of process options, and has many more players both at the foundry side and the design side.

The key enabling technologies for the IoT market are extremely low power as enabled by SOI and sub-threshold design, integrated with multiple sensor and communication technologies that are both enabled by 3D integration. All of these combine in forming the IEEE S3S unified conference.

This year’s conference includes many exciting papers and invited talks. It starts with three plenary talks:

  • Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  • Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  • Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration

The following forecast from BI Intelligence suggest that the semiconductor technologies that are a good fit for the future market of IoT should be of prime interest for the semiconductors professional.

S3S_BI

Jim Walker, Research VP at Gartner, argued at the “Foundry vs. SATS: The Battle for 3D Wafer Level Supremacy” market symposium that 3D ICs are the key enabler of performance and small form factor of products required for IoT.

The upcoming IEEE S3S conference provides an important opportunity to catch up and learn about these technologies.

Let me share with you some nuggets from the monolithic 3D integration part of the conference:

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” which will present a process technology to fabricate flexible devices 6-20 microns thin. This process flow is currently in manufacturing in their Stuttgart fab, as depicted below:

S3S_Fig3

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor”. These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

In his invited talk “Emerging 3DVLSI: Opportunities and Challenges” Dr. Yang Du will share  Qualcomm’s views on monolithic 3D IC, which they term 3DVLSI and illustrate below, which seems very fitting for IoT applications.

S3S_Fig2

Globalfoundries will present joint work with Georgia Tech on “Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”. This work again shows that monolithic 3D can provide a compelling alternative to dimensional scaling as illustrated by the following chart.

S3S_Fig4

Monolithic 3D will present “Modified ELTRAN (R) – A Game Changer for Monolithic 3D” that shows a practical flow for existing fabs to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. The following slide illustrates the original ELTRAN flow.

S3S_Final

By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short courses on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future.

In 2014, the automotive sector significantly outperformed the overall market average for semiconductors. In fact, the automotive market overtook data processing to become the third largest end market for power semiconductor applications, according to IHS Inc., a global source of critical information and insight.

Based on information from the IHS Power Management Market Share and Supplier Analysis report, demand for semiconductors by the automotive industry was particularly strong in advanced driver assistance systems (ADAS) and infotainment systems. In the power management semiconductor market, power integrated circuits (ICs) grew much faster than traditional power discrete solutions. The automotive power IC category in 2015 is forecast to grow 8 percent, year over year, while discrete revenue is projected to remain flat during the same time period.

Fig 1

Fig 1

“One strategy that automakers are undertaking to control research and development costs is to develop shared designs, components, engineering, and production platforms, and using the same electronic control units (ECUs)  for many different platforms with the same features,” said Jonathan Liao, senior analyst of power semiconductors for IHS. “While over time modern cars have increased in size, suppliers prefer small and interchangeable electronic control units that can fit on various platforms, which help lower overall development costs, and expand the universe of target customers, for an improved return on investment.”

As a result of this approach, automotive power ICs are growing faster than discrete solutions. For example, Texas Instruments – the market leader in voltage regulators — controlled 8 percent of voltage regulators used by the automotive industry in 2011 and increased its voltage regulator revenues by 150 percent by the end of 2014. By comparison, Infineon — the leading automotive-market supplier of discrete power solutions — increased their power management revenues, at roughly half of Texas Instruments’ growth rate, during the same time period.

Growing demand for luxury features in non-luxury vehicles

Increased consumer demand has caused many luxury car features to find their way into the non-luxury car market, which is causing an increase in overall demand for power ICs. Adaptive cruise control, blind-spot monitoring, connected traffic updates, sophisticated infotainment systems with voice command and other advanced features are being integrated, as both options and upgrades, into mass-produced mid-range vehicles, like the Ford Fusion, which has a suggested price of $22,000. “Features that were originally designed for Mercedes-Benz, BMW, Lexus and other luxury cars have very quickly found their way into the non-luxury market,” Liao said

There are several key features that will encourage further power IC adoption, including Internet-connected cars, vehicle-to-vehicle (V2V) communications, autonomous cars, Apple’s CarPlay and Android Auto. For all of these features, application processing speed and software are critical components.

“It is crucial for the ECUs to gather, process and respond to information in real time, for the safety and convenience of the driver,” Liao said. “Sophisticated power management solutions for power-intensive multi-core processors, baseband chipsets and sensor arrays can be implemented much more easily with power ICs.”

All of these advanced features are expected help power ICs to grow faster than discrete solutions.

The overall trend of power ICs outperforming power discrete solutions in the automotive semiconductor sector is expected to continue. Switch regulators, low-dropout (LDO) regulators and power management integrated circuits (PMICs) are examples of fast-growing power IC components with better integration, efficiency and smaller footprints –especially for low voltage applications in automotive electronics.

SEMICON Taiwan 2015 opened today starting a three-day event drawing over 43,000 attendees from electronics manufacturing. Held 2-4 September, SEMICON Taiwan represents the huge Taiwan business potential with Taiwanese chipmakers and Outsourced Semiconductor Assembly and Test (OSAT) firms spending over $20 billion in the next two years on equipment and materials.

2015 is the 20th anniversary of SEMICON Taiwan and now draws more than 700 exhibitors and more than 43,000 attendees.  Over 500 will attend the SEMICON Taiwan Leadership Gala Dinner, one of the most important executive events for the high-tech industry in Taiwan.

SEMICON Taiwan features co-located events and technology theme pavilions focusing on IC design, MEMS, 3D-ICs, advanced packaging/testing, sustainable manufacturing, and secondary equipment.

Highlights of this year’s show include:

  • Executive Summit: With the theme “Conversation between Nobel Prize Laureate and Distinguished Leaders in Taiwan,” executives from Executive Yuan, Etron Technology, ASE Group, and NCTU will share their unique perspectives with Prof. Shuji Nakamura, 2014 Nobel Prize winner.
  • Market Trends Forum: Forum features speakers from Beijing Gaohua Securities, IDC Asia/Pacific, UBS Investment Bank, Sanford C. Bernstein, TechSearch, and SEMI, with moderation by TSMC.
  • CFO and Investor Summit: With the theme, “An Exciting Period of Growth and Mergers in the Semiconductor Industry,” the event features speakers from TSMC, DBS, National Tsing Hua University, imec, and Taiwan M&A and Private Equity Council, with moderation by EQUVO.
  • Memory Executive Summit: The Summit includes presenters from Everspin, imec, Inotera Memories, and ITRI.
  • SiP Global Summit 2015: With a strong focus on heterogeneous integration through System-in-a-Package (SiP) technology, the event features more than 20 industry leaders who will share their insights and solutions on 3D-IC, Through Silicon Via (TSV), 2.5D-IC with silicon interposer, and embedded substrate technologies. More than 500 industry professionals from around the world are expected to attend.
  • Advanced Packaging Technology Symposium: Presenters will cover market trends, product applications, and packaging/assembly solutions to advanced equipment and material development, and testing and reliability – covering the most advanced technology development directions for 3D-IC.
  • Sustainable Manufacturing Forum: Experts will address a wide variety of environment, health, safety (EHS) and sustainability topics that affect high-tech manufacturing.
  • Semiconductor Materials Forum: This is the newest forum — features topics including front-end materials for advanced semiconductor devises, advanced materials solutions for 10nm and beyond, challenges for local material manufacturers, and novel materials, and activities for advanced packaging.

For more information and online registration, visit the SEMICON Taiwan website: www.semicontaiwan.org

At the 65th IEEE ECTC, several companies presented advances in thermos-compression bonding.

BY PHIL GARROU, Contributing Editor

Jie Fu of Qualcomm discussed “Thermal Compression Bonding for Fine Pitch Solder Interconnects.” Mass reflow-based interconnects, using either solder bump or Cu-column on bond on lead are the typical low-cost flip chip assembly approaches used by industry. These interconnects face challenges related to shorting and non-wets at sub 100μm pitches.

Transitioning below 100μm pitch requires a new approach, such as thermos- compression flip chip (TCFC). While TCFC provides higher accuracy bonding and allows for use of smaller solder cap which enables tighter FC pitch, it also presents new challenges. The major challenges for TCFC bonding include lower throughput and control of non-conductive paste (NCP) voids.

Overall, bond head ramp rate, temperature uniformity, peak temperature and dwell time must be fine-tuned in tandem to compensate for manufacturing tolerances and to get the desired end of line solder joint structure. In addition, controlling the temp exposure for the NCP material before NCP cure is critical to enable a robust TCFC solder joint. Too much thermal exposure and the NCP begins to cure prior to solder melting, which can leading to NCP entrapment and unreliable TCFC solder joints. Laminate surface finish is also an important variable.

In a similar study Cho and co-workers at GlobalFoundries presented “Chip Package Interaction Analysis for 20-nm Technology with Thermo-Compression Bonding with Non-Conductive Paste.” Strong market demand for finer pitch interconnects to enable higher I/O counts in a smaller form factor is driving another transition from conventional MR bonding process to thermo-compression bonding using non-conductive paste (TC-NCP). FEA simulation results for TC-NCP vs mass reflow show that TCNCP has significantly reduced thermomechanical stress at the ULK level and the bump level.

Horst Clauberg of K&S discussed “High Productivity Thermo- compression Flip Chip Bonding.” There is tremendous effort by IDMs, OSATs, materials suppliers and equipment suppliers to bring thermos-compression bonding to commercial reality. The most significant technical challenges have for the most part been solved and limited commercial production is taking place. However, relatively low throughput and high equipment cost create adoption resistance, especially in the all-important consumer market.

Thermocompression bonding can be segmented into two different processes. The first process differentiation is whether the underfill is pre-applied before the semiconductor chip is mounted or not. Pre-applied underfill comes either as a film applied to the die or as a paste applied to the substrate. In both cases the underfill must not only create a void-free bond, but also provide flux to remove oxide on the solder caps. The alternative process is thermocompression – capillary underfill (TC-CUF) where the die is underfilled in the same way as standard flip chip, except that the underfill process is much more challenging because of the more narrow bondline of a typical thermocompression bonded device. In TC-CUF, flux can be applied either by dipping the die into flux before bonding, or applying flux to the substrate.

Doug Hiner in a joint presentation between Qualcomm and Amkor presented “Multi-Die Chip on Wafer Thermo-Compression Bonding Using Non-Conductive Film.” Non-conductive films have been in development as a replacement to the liquid preap- plied underfill materials used in fine pitch copper pillar assembly.

Several assembly methods are available for chip on wafer assembly including: (1) traditional chip attach with mass reflow (MR) and capillary underfill (CUF), (2) thermo-compression bonding (TCB) of copper pillar interconnects using noncon- ductive paste (NCP) underfill (TCB+NCP), and thermocom- pression bonding of copper pillar with non-conductive film (NCF) underfill (TCB+NCF).

The TCB+NCP process carries concerns with the underfill time on stage which prevents the dispensing of the NCP material across the wafer prior to the chip bonding process. This constraint effects process costs significantly. The TCB+NCF process to date have not met the cost/benefit needs of the industry. NCF assembly provides significant improve- ments in the design rules associated with die to package edge, die to die, and fillet size. The NCF process also resolves the time on stage concerns associated with the NCP process by laminating the NCF material to the bonded die instead of to the interposer or receiving wafer surface.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that the company is experiencing strong demand for its automated 300mm polymer adhesive wafer bonding systems. Over the past 12 months, the company’s order intake has doubled for these systems, including the EVG 560, GEMINI and EVG 850 TB/DB series of wafer bonders. This includes multiple system orders from leading foundries and outsourced semiconductor assembly and test (OSAT) providers headquartered in Asia. Much of the increase in demand is being fueled by advanced packaging applications, where manufacturers are ramping up production of CMOS image sensors as well as vertically stacked semiconductors incorporating 2.5D and 3D-IC through silicon via (TSV) interconnect technology.

According to market research and strategy consulting firm Yole Developpement, the equipment market for 3D-IC and wafer-level packaging (WLP) applications is expected to grow significantly, from $933 million in 2014 to $2.6 billion in 2019 (total revenue), at a compound annual growth rate of 19 percent over the next five years*. Adhesive wafer bonding plays a critical role in supporting these applications.

Automated adhesive wafer bonding enables high yields on stacked devices
Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates, which is an important process technology for advanced packaging applications. The main advantages of using this approach are low temperature processing, surface planarization and tolerance to wafer topography. For CMOS image sensors, polymer adhesive bonding provides a protective barrier between the surface of the image sensor and the glass cover wafer. For 3D-IC TSV applications, polymer adhesive bonding plays an important role in temporary bonding and debonding applications, where product wafers are temporarily mounted on carriers with the aid of organic adhesives to enable reliable thinning and backside processing.

For both CMOS image sensor and stacked memory/logic applications, fully automated wafer bonding solutions are essential to support manufacturers’ migration to larger (300mm) wafer substrates to lower their overall cost of production. For example, minimizing total thickness variation (TTV) of the adhesive layer after bonding is crucial in defining the final product thickness tolerance. This ultimately has an impact on enabling thinner wafers and devices, which in turn enableshigher interconnect densities and lower TSV integration costs. EVG’s automated wafer bonding systems provide superior control of TTV and other parameters through repeatable wafer-to-wafer processing and integrated inline metrology to monitor TTV throughout the bonding process. As a result, manufacturers are increasingly turning to EVG to support their automated wafer bonding needs.

“We’ve truly entered the era of 3D-ICs, with demand for TSV wafers rising on a number of fronts—from CMOS image sensors for smart phone cameras and automotive surround view imaging, to 3D stacked memory and memory-on-logic to support high-performance, high-bandwidth applications such as networking, gaming, data centers and mobile computing,” stated Hermann Waltl, executive sales and customer support director at EV Group. “Automated wafer bonding is a critical process for supporting the volume manufacturing needs of CMOS image sensor and semiconductor device makers addressing these applications. EVG has invested years in the development of wafer bonding technology to make it a critical value-add solution for the advanced packaging market. Our breadth of knowledge in wafer bonding equipment and processes—along with our strong network of supply chain partners—has positioned us well to anticipate future industry trends and develop new solutions that meet our customers’ emerging production requirements.”

Tessera Technologies, Inc. today announced the acquisition of Ziptronix, Inc. for $39 million in cash. The acquisition expands on Tessera’s existing advanced packaging capabilities by adding a low-temperature wafer bonding technology platform that will accelerate delivery of 2.5D and 3D-IC solutions to semiconductor industry customers.

Ziptronix’s patented ZiBond direct bonding and DBI hybrid bonding technologies deliver scalable, low total cost-of-ownership manufacturing solutions for 3D stacking. Ziptronix’s intellectual property has been licensed to Sony Corporation for volume production of CMOS image sensors – an estimated $8.3 billion market according to Gartner. Ziptronix’s technology is also relevant to next-generation stacked memory, 2.5D FPGAs, RF Front-End and MEMS devices, among other semiconductor applications. Inclusive of CMOS image sensors, Tessera expects the annual market size to which this technology applies to exceed $15 billion by 2019.

“With this acquisition we’re gaining best-in-class technology, along with exceptional people, know-how in the 3D-IC market and a significant patent portfolio,” stated Tom Lacey, CEO of Tessera. “With the escalating cost for each node of semiconductor lithography, it remains very clear to us that our R&D spend on semiconductor packaging will only become more important and valuable to our customers. Ziptronix has commercially licensed the ZiBond and DBI technologies and they stack up very well alongside our extensive portfolio of 2.5D and 3D intellectual property. I’m confident that aligning our respective capabilities with our development expertise will help create a multi-hundred million dollar revenue opportunity for Tessera over the next decade as the industry continues to shift toward 3D-IC architectures.”

“ZiBond and DBI bonding are enabling technologies that provide significant cost and performance benefits,” said Craig Mitchell, President of Invensas, a Tessera subsidiary. “There is a great opportunity to further develop these platforms with our technology partners, and we’re very excited about their market potential.”

Founded in 2000 as a venture-backed spinoff of RTI International, privately held Ziptronix is a pioneer in the development of low-temperature direct bonding technology for 3D integration. Ziptronix is headquartered in Raleigh, North Carolina.

Dan Donabedian, President and CEO of Ziptronix added, “We’ve taken our technology from concept to commercialization in the backside illuminated image sensor and RF markets. Joining the Tessera family of companies combines our efforts with a proven leader in technology development and licensing in the semiconductor industry. This is a great alignment of companies that can address rapidly expanding 2.5D and 3D-IC markets.”

The addition of the Ziptronix team will not change Tessera’s target operating expense structure. Tessera is making no adjustments to third quarter 2015 revenue or earnings per share guidance.