Category Archives: Semicon West 2013

Developers have made major progress in the technology to manufacture printed or flexible circuits, sensors, batteries and displays. But frankly it’s been hard to build applications with much market pull without logic or memory as well, and those have been much harder to make. However, now printed memory and solutions for integrating conventional silicon die into flexible systems are edging into production, to potentially improve performance for a wider range of applications.  On the display side, easily integrated printed or flexible transparent conductive films for touch screens are starting to see some market traction.

Yole Développement projects the market for printed and flexible electronics will remain a modest ~$176 million this year, but will see 27 percent CAGR to ~$950 million by 2020, driven largely by printed layers integrated into large OLED displays.

Thinning patterned die makes flexible silicon on polymer

One interesting solution to add performance to flexible electronics could be an open platform for making flexible silicon die. American Semiconductor proposes drastically thinning conventional fabricated silicon wafers, and coating them with a combination of polymers. The resultant silicon-on-polymer approach protects and eases handling of the ultra-thin die, says CEO Doug Hackler, who will discuss the technology in a program on such hybrid solutions in the emerging market program series at SEMICON West in San Francisco in July. He reports user interest for large area distributed sensing systems that include ICs within structural composites in aircraft bodies to monitor stress, for bio sensors that conform to the body, for RF for wireless data transmission from printed sensors, and for drivers for flexible displays.

The company has qualified TowerJazz’s 130nm process to make SOI CMOS for its initial flexible standard microcontroller, and has worked with the foundry to establish design rules to make an open platform for other designers to create their own flexible chips. American Semiconductor thins these fabricated wafers by standard methods down to about ~40µm. “And then from <40µm it gets trickier and more proprietary,” says Hackler. But once these flexible silicon-on-polymer die are diced and released, they can be handled pretty much like standard chips. “The dicing and release are a little different, but once the die are on tape, then it appears feasible to do traditional pick and place,” he says, noting the company intends to use printed connections instead of bonding wire or solder bumps. After assembly on a flexible substrate, perhaps by a pick-and-place module integrated on a roll-to-roll printing tool, the devices would typically be laminated or overcoated for additional protection. The company plans to follow its flexible microcontroller with a standard analog/digital converter to take in sensor data, and an RF IC to send out the data. 

Innovative solutions for assembling silicon on flexible substrates move towards production

Packaging and assembling tiny thin die on flexible substrates remains a challenge, but multiple suppliers are making progress towards solutions that are starting to edge into commercial production. One approach particularly suitable for attaching sensors to the body is the spring-like stretchy wiring developed by MC10 for attaching thin silicon die to flexible substrates, for everything from wearable heart rate and fitness monitors to sensor membranes that can be implanted directly on organs inside the body. VP of R&D Kevin Dowling reports the company’s first commercial application is in a soft skullcap from Reebok that uses flexibly connected motion sensors to measure impacts to the head.

Tiny die size could also help with both cost and attachment of rigid die to conformable substrates, although handling and assembling them then becomes more of an issue. Terepac Corp. CTO Jayna Sheats notes that plenty of logic for simple controls could be very tiny and low cost — microprocessors with ~8000 transistors like the Z-80 generation currently used for many embedded control applications take up  <70µm2 of silicon with 90nm design rules, for millions on a wafer. But the die are too tiny to make the input/output connections or to handle with traditional pick and place for packaging and assembly. So Terepac proposes a photochemical assembly process instead, picking up an array of thinned and diced chips with a sticky printhead, positioning the chips over the substrate with a tool similar to a proximity aligner, and vaporizing the proprietary polymer/adhesive behind each selected chip with a combination of heat and UV so it falls into the desired position.  Chips can then be attached to the flexible substrate by conductive adhesive, electroplating, or printed connections. The company is working with equipment manufacturing partners including Rockwell International to construct manufacturing facilities for customers with products for the Internet of Things.

Jabil reports progress in low temperature attachment technologies for use with heat-sensitive flexible substrates. And Sandia National Lab reports it’s come up with a solution for the common researchers’ problem in this field of how to build prototypes of flexible systems when the necessary ultra thin chips only come in costly wafer-level volumes. Researchers there have figured out how to thin off-the-shelf single die for developing flexible systems.

Printed memory targets low-cost, high-volume applications          

Thin Film Electronics, meanwhile, is developing systems that use its simple, low cost printed memory. The company’s 20-bit memory can be produced in volume for under ~$0.05, targeted at applications like consumer packaging, with volumes of billions of units a year where roll-to-roll printing makes most sense, says Chandrasekhar Durisety, assistant director, North America, who will give an update on the company’s progress towards commercialization at the session. Thin Film is introducing a next generation of passive array memory, in 4×4 (16 bit), 5×5 (25 bit) or 6×6 (36-bit) options, a more conventional format with fewer pads at higher density for easier addressing than its initial 20-bit in-line architecture. 

The company is working with a global consumer product maker on using low-cost printed memory to make brand authentication cost effective for a wide range of lower-priced products. It’s also working with major flexible packaging supplier Bemis Company Inc. on sensor labels for food, healthcare and consumer products that can collect and wirelessly communicate sensor information at roughly the same low cost as current color-changing chemical indicators. The digital system under development — with Thin Film’s printed memory, an electrochromic display from Acreo, and printed logic technology from PARC — stores data when the temperature exceeds a certain range, to indicate more clearly than a color gradient can whether the product is usable or not. 

Thin Film aims to add electronics to applications that currently don’t use them, to add simple intelligence at prices far below those possible with silicon, such as low-cost brand authentication, temperature sensors on packaging, or simple electronics in toys.  “Silicon die could add significant capability to printed electronics. But with fabrication and assembly it would likely be more expensive than either silicon or printed electronics alone,” suggests Durisety.”  

Market starts to develop for printed/flexible ITO replacements

Another key potential market for printed/flexible electronics is next-generation transparent conductive film to replace brittle and expensive indium tin oxide in touch screens and displays, lighting, and photovoltaics.  Touch Display Research says the market for non-ITO transparent conductors will be about $206 million this year, and grow to some $4 billion by 2020.  “High demand for touchscreens for notebook and PC size displays has created a shortage of ITO touch sensors since the end of last year to drive more interest in these technologies, and the more flexible and potentially cheaper replacement technologies are getting more mature,” notes Jennifer Colegrove, president and analyst, who will speak at the FlexTech workshop on transparent conductors. She notes that Atmel, FUJIFILM, Unipixel and Cambrios are all in some phase of production.

There is, however, a confusing range of contending options for processes and materials for these films.  Applied Materials has interesting progress in its roll-to-roll deposition technology, while FUJIFILM Dimatix targets ink jet printing the materials, and NovaCentrix offers rapid thermal curing that doesn’t heat the substrate. Materials options range from nano metal wires at Cambrios Technology, Carestream and Sinovia, to embossed and metalized patterns from Unipixel, to carbon nanotubes at Brewer Science and graphene at Nanotech Biomachines. 

These and other speakers will talk about the challenges and solutions to move printed/flexible electronics into real markets at SEMICON West’s emerging technology programs, July 9-11 in San Francisco.

· Mon, July 8: Market Symposium, SF Marriott Marquis, Keynote: “New Directions in Flexible and Printed Electronics,” Dr. Ross Bringans, VP at PARC (1:00-5:30pm)

· Tue, July 9: Materials Growth Opportunities at Both Ends of the Spectrum (1:30-3:30pm)

· Wed, July 10: FlexTech Alliance Workshop: Emerging Materials and Processes for Transparent Conductors, SF Marriott Marquis (10:00am-5:00pm)

· Thur, July 11: Integrating Conventional Silicon in Flexible Electronics at the Extreme Electronics TechXPOT, South Hall (10:30am-1:10pm)

For more information, visit www.semiconwest.org/SessionsEvents/PlasticElectronics

Paula Doe is an analyst for advanced technologies for the global trade association SEMI.

Multitest’s James Quinn will present during the 2013 SEMICON West exhibition and conference, scheduled to take place July 9-11, 2013 at the Moscone Center in San Francisco, CA. The presentation, entitled “Quality in 3D Assembly- Is KGD Enough,” will enable the audience to understand the additional risks of 3D assembly and match them with their own situation.

Quinn will provide an overview of the current discussion in the industry and how to manage the risks of 3D assembly. Also, the audience will learn more about the special requirements of the new approaches and understand their pros and cons. The audience will be able to apply the presented concepts to their own 3D business models. The most appropriate equipment will be discussed: What are the limitations of using probing tools or deploying final test equipment? Which strategy will offer the most synergies and reduce cost of test in the end? Finally, an analogy with the MEMS will give an interesting perspective on how to leverage the expertise that has been gained during the last decade.

Quinn is the VP of Sales and Marketing at Multitest. He has a strong semiconductor background and has served as executive VP responsible for sales and marketing at respected companies including Süss Microtec AG, MD of Süss Microtec Inc. in the U.S., and most recently as CEO of a venture capital wafer front-end equipment company in Sweden and France. Quinn studied business administration and marketing at San Francisco State University.

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, today reported that worldwide semiconductor manufacturing equipment billings reached US$ 7.31 billion in the first quarter of 2013. The billings figure is 8 percent higher than the fourth quarter of 2012 and 32 percent lower than the same quarter a year ago. The data is gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 100 global equipment companies that provide data on a monthly basis.

Worldwide semiconductor equipment bookings were $7.78 billion in the first quarter of 2013. The figure is 23 percent lower than the same quarter a year ago and 14 percent higher than the bookings figure for the fourth quarter of 2012.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Book-to-Bill Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Semiconductor Equipment Consensus Forecast, which provides an outlook for the semiconductor equipment market.

Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.  To address these massive changes, SEMICON West will feature a number of programs on new packaging technologies and processes with speakers from leading chip makers, equipment manufacturers, and material suppliers.

According to IDC, forecasts semiconductor revenues will log a compound annual growth rate (CAGR) of 4.1 percent from 2011-2016, but revenues for 4G phones will experience annual growth over 100 percent for the same period. NanoMarkets estimates that the global market for “Internet of Things” sensors will reach $1.6 billion this year and grow to a value of $17.6 billion by the end of the decade as sensors become increasingly connected to the Internet directly or through hubs.  Both trends will significantly impact semiconductor and microelectronics packaging.  Demand for equipment and related tools in the 3D-IC and wafer-level packaging area alone is forecasted to grow from approximately $370 million in 2010 to over $2.5 billion by 2016, according to Yole Developpment.

To address these changes, SEMICON West 2013 (register at www.semiconwest.org/registration), held on July 9-11 in San Francisco, will feature a number of programs on new packaging applications, requirements, technologies, and products, including:

  • Generation Mobile:  Enabled by IC Packaging Technologies — Speakers from ASE, UBM Tech Insights, Amkor Technology, SK Hynix, and Universal Scientific Industrial will present on the latest advances in wafer-level packaging, new materials, and multi-die integration, including new System-in-Package (SiP) and Package-on-Package (PoP) methods. Location: Moscone Center (North Hall), TechXPOT North, Tuesday, July 9, 10:30am-12:30pm.
  • “THIN IS IN": Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era — IEEE/CPMT will hold a technical workshop on the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs with speakers from Intel, Cisco, ASE, Micron, SK Hynix, Nanium, Kyocera and more. Location: San Francisco Marriott Marquis, Tuesday, July 9, 1:30-4:45pm.
  • Advancing 2.5D and 3D Packaging through Value Engineering — Speakers from Altera, Amkor, ASE, ASET, KPMG, UMC, STATS ChipPAC and more will take a critical look at 2.5D implementations and the current outlook for 3D packages, including tools and technologies for heterogeneous stacks. Location: Moscone Center (North Hall), TechXPOT North, Wednesday, July 10, 1:00-3:30pm.
  • MEMS & Sensor Packaging for the Internet of Things— This session will feature speakers from all parts of the ecosystem to address how future visions of a pervasive interconnected world will be realized through the heterogeneous integration of MEMS and ICs.  The program will feature keynote speaker Janusz Bryzek from Fairchild Semiconductor, and speakers from VTT Research, Fraunhofer IZM, Robert Bosche, EV Group, Dai Nippon Printing, and more. Location: Moscone Center (North Hall), TechXPOT North, Thursday, July 11, 10:30am-1:00pm.

In addition to the packaging programs, SEMICON West 2013 will also feature over 560 exhibitors with the latest innovation on microelectronics manufacturing, including over 150 exhibitors with equipment and technology solutions for advanced packaging.  Other programs and exhibitors at West will address lithography, advanced materials and processes, silicon photonics, test, LED and MEMS manufacturing, and other subjects.  For more information on SEMICON West and to register, visit www.semiconwest.org

Much has been said of the 450mm transition.  But the description of this inflection is something of a misnomer.  Though everyone desires a smooth, coordinated and orderly conversion, it may be a little less placid than the term “transition” implies.  Rather, I suggest calling it the 450mm “transformation.”   Because, even for the segments that continue manufacturing semiconductor devices on 300mm and 200mm silicon wafers, the industry will change dramatically with the introduction of 450mm wafer processing. The 450mm era will impact industry composition, supply chain dynamics, capital spending concentration, future R&D capabilities and many other facets of today’s semiconductor manufacturing industry — not the least of which are the fabs, wafers and tools with which chips are made.

The shift to 450mm will take a several years to manifest and numerous complexities are being skillfully managed by multiple organizations and consortia.   For those reasons, the evolutionary tone of “transition” seems appropriate. However, once the changeover occurs, in hindsight, most in the industry will recognize that they participated in something transformational.

No transformation occurs in isolation and other factors will contribute to the revolutionary qualities of 450mm.  Market factors, new facilities design, next generation processing technology, the changing dynamics of node development and new materials integration will simultaneously affect the industry landscape.

While reading about the implications of 450mm is valuable, I believe that there is much to learn by being a part of the discussion. How is this future transformation being envisioned and acted on today?  I hope that you will join us — at our “live” event, where you will have the opportunity to hear first-hand information… direct from well-informed experts in the industry.

SEMICON West offers this opportunity with “Must See” 450mm events to mark on your calendar…

….450 Consortia plans, timelines and status; equipment development; critical standards; future-looking fab facilities and EHS issues; executive perspective, and vital R&D capabilities will all be covered at SEMICON West.

Wafer Standards

The transition to 450mm manufacturing is accompanied by the development of various standards aimed at achieving cost, efficiency and technology improvements. Some standards are a product of the deliberate consensus-based SEMI International Standards program, which has produced over 15 essential 450mm-specific standards to-date.  Additionally, consortia, customers and suppliers organize complementary efforts to align common approaches to transition solutions.

Potential revisions in the 450mm wafer specification are under consideration.  At least two issues are currently being evaluated by the industry and both portend significant ramifications for wafer suppliers, equipment makers and those technologies that interface with the wafer.

First, the wafer orientation method may be revised to eliminate the orientation “notch” on the perimeter of the substrate. The notch was introduced in the 300mm transition as an alternative to the flat.  However, both equipment suppliers and IC makers, through a constructive and collaborative dialog, have concluded that eliminating the notch can potentially improve the die yield, tool performance and cost.

Secondly, reduction of the wafer edge exclusion area — that peripheral portion of the silicon on which no viable device structure occurs — also offers potential yield advantages.  The current 450mm wafer specification (SEMI E76-0710), originally published in 2010, calls for a 2mm edge exclusion zone.  IC makers believe that reduction of this area to a 1.5mm dimension offers the cost equivalence of a 1 percent yield increase.  Though a percent may sound trivial, it is represents substantial increased value over time.

These and other wafer-related issues will be key topics at SEMICON West and will be thoroughly reviewed on Wednesday, July 10 at the SEMI Standards program entitled “Silicon Wafers — Future Standardization to Enable the Transition.” Materials will be presented by expert speakers including authoritative customers participating in the Global 450 Consortium (G450C), which includes Samsung, TSMC, IBM, Intel and GLOBALFOUNDRIES.

Facilities and EHS

Wafer transitions offer one of the rare periods when new approaches can be developed and integrated into facilities plans.  During the 300mm transition, significant developments occurred in factory automation and wafer handling. Similarly, the 450mm transition is a window to update the industry approach to a number of fab systems. Rising energy costs, water scarcity, and climate change will continue to present both challenges and opportunities for semiconductor manufacturing in the 450mm era. These sustainability concerns are driving demand for tools that can more reliably and cost-effectively achieve a shared vision of resource balance.

Along with cost and efficiency improvements, IC makers and consortia driving the transition to 450mm manufacturing expect to achieve similar or better environmental performance. Larger footprints and resource demands from 450mm facilities in conjunction with mandates for environmentally aware operations are compelling fabs and suppliers to consider sustainability and systems integration at greater levels than ever before. 

Experts in fab facilities, energy, water and equipment engineering will discuss the implications of 450mm to environment, health and safety during the SEMICON West 450mm Manufacturing EHS Forum on Wednesday, July 10.

Included in the presentations are perspectives from the Facility 450 Consortium (F450C) including Ovivo, Edwards and M+W Group.  A holistic Site Resource Model that provides semiconductor manufacturers visibility into effective reduction of total energy and water demands for individual systems, as well as for the entire facility will be reviewed by CH2M Hill. The model is an integrated analytical approach to assess and optimize a semiconductor facility’s thermal energy, electrical energy, and water demand, as well as the cost associated with these resources.

Also, the bigger, heavier and taller equipment envisioned for 450 entails new considerations for installation, movement and maintenance.  Making sure these issues don’t detract from the other cost saving achievements is a key consideration for facilities planning.  G450C representatives will review the status of component lift analysis currently underway. The solutions potentially alter fab facilities dimensions, tool engineering and service regimes.

450 TechXPOT

The SEMICON West 450mm Transition Forum covers the latest updates from those closest to the action.  The event occurs on Thursday, July 11 at the South Hall TechXPOT located in Moscone Center.  Paul Farrar, general manager of Global 450mm Consortium will provide an update and status on G450C. Hamid Zarringhalam, executive vice president, Nikon Precision, will review the challenges and status of 450mm lithography — which is shaping up to be one of the most uncertain yet critical 450mm planning considerations. Chris Richard, a partner at PricewaterhouseCoopers, LLC will talk about “Improving Semiconductor Equipment Vendor Profitability during the 450mm Transition.”

Then, SEMI will host a discussion among the world’s foremost 450mm tool experts from leading equipment companies.  The discussion panel will include: Kirk Hasserjian, corporate vice president, Silicon Systems Group, Applied Materials, Inc., Brian Trafas, Ph.D., chief marketing officer, KLA-Tencor; Mark Fissel, vice president, 450mm Program, Lam Research Corporation; and Akihisa Sekiguchi, Ph.D., vice president and general manager of SPE Marketing, Tokyo Electron Limited.  We have a few provocative topics to review with panel members.  If you have questions or topics you want addressed by those at the front line of the 450mm transformation, feel free to send us your suggestions.

In summary, a transformation will occur in IC manufacturing with the introduction of larger wafers, but it begins with serious engineering that is occurring now.  Attend SEMICON West to learn more about wafer specifications, EHS and facilities— considerations and business strategies for success and be better prepared for the numerous implications of 450mm era.

Learn more about it here: www.semiconwest.org. Register now at www.semiconwest.org/registration.

 

 

Critical trends and developments in the technologies, methodologies, and applications challenges in semiconductor test will be presented at the 6th annual IEEE Test Vision 2020 Workshop held in conjunction with SEMICON West 2013, on July 10-11 at the San Francisco Marriot Marquis Hotel. The one and one-half day workshop will feature speakers from Flextronics, Broadcom, Qualcomm, Texas Instruments, AMD, ON Semiconductor, Mentor Graphics, Micron, along with those from key semiconductor test industry suppliers. Organized by SEMI and sponsored by the IEEE Instrumentation and Measurement Society, Test Vision 2020 is a two-time winner of the ATE Test Technology Technical Council’s “Most Successful Event” Award.  Registration for Test Vision 2020 is now open at www.testvision2020.com, and includes free admission to SEMICON West.

Test Vision 2020’s purpose is to facilitate learning, forecasting and debate on the future of semiconductor test and serves as a valuable platform where leading foundries, IDMs and fabless companies discuss their critical test requirements with leading test equipment and solution providers.  This year’s program will feature panel discussions and leading industry experts that focus on the following key questions:

  • How can we achieve faster time to market with lower product costs?
  • What are the Test challenges in emerging technologies?
  • How much Test is enough?
  • What are the possible paths to economical high-speed test?
  • What are the next big innovations in Semiconductor Test?
  • What will be the new skills and competencies needed by future test engineers?

The keynote speaker for Test Vision 2020 will be Dr. Erik Volkerink, chief technology officer at leading end-to-end supply chain powerhouse, Flextronics.  He will present on the topic, “Product Foundry: Next Paradigm in Product Design and Engineering.” Featured speaker will be Sri Jandhyala, Strategic Marketing Director for ON Semiconductor, whose presentation will be, “LED Lighting — Opportunities, Challenges and the Future.”  Leading test equipment and solution providers will also highlight the latest test developments and trends, including speakers from Advantest, LTX-Credence, Roos Instruments, and Teradyne.

Starting at 3:00 p.m. on Wednesday, July 10 and concluding at 4:45pm on Thursday, July 11, Test Vision 2020 will also include a networking and casual social event on Wednesday evening.

Several years ago when the challenges to 450mm wafer processing, EUV development and novel transistor designs were first being discussed, SEMI commissioned a study that predicted the industry could face an R&D funding gap that could exceed $9 billion if current technology and economic trends continue. At the time, SEMI issued a statement saying the industry was at a “crossroads” and “without significant attention to the R&D gap, the semiconductor equipment and materials industry will not be able to afford to keep up with Moore’s Law.”

technology forum

Much has happened since that report was issued: 450mm development was delayed, but now is ramping at G450C; Intel, Samsung and TSMC have invested over one billion dollars in ASML; cost targets have been missed at 28nm; and 3D-ICs have emerged as an alternative development path for leading-edge chip solutions.  But the R&D challenges remain.   The industry has responded in unexpected and unique ways, including new funding models, new consortia programs, increasing joint development agreements, and other mechanisms.  How R&D processes and strategies have evolved, and will probably continue to evolve, will be the subject of several programs at SEMICON West.

The most significant trend in R&D in the industry, and increasingly important to the supply chain, is the growth and changing role of R&D consortia.  Not long ago, the top research organizations served the advanced research needs of IDMs.  Today, equipment and material suppliers, EDA software providers, fabless chip companies, and other diverse organizations participate in consortia initiatives.  In the near future, there may be increasing involvement from system companies like Apple, Cisco, and Google.  Along with changes in participation, the types of research conducted by consortia have also evolved, many directly involving component and subsystem suppliers. Today, there are consortia that specialize in key areas like wafer size transition and lithography, but also many of their programs seem to overlap, potentially creating inefficiencies and redundancies in R&D efforts that consortia were supposed to eliminate.

Many of these issues will be discussed in a special executive panel on semiconductor R&D at SEMICON West.  On Wednesday, July 10, I will be joined on stage by Daniel Armbrust, president and CEO of SEMATECH; Michael Liehr, executive VP at CNSE; Dr. Laurent Malier, CEO of CEA-Leti; and Dr. Luc Van den hove, president and CEO of imec to discuss the critical trends and developments in R&D and how they will affect SEMI members.  We will discuss the important role of consortia and what’s new at their organizations, but also share our perspectives on the changing role of the R&D engineer and scientist in the industry today.  Increasingly, R&D is becoming more about managing complex multi-organization processes and innovation platforms than it is about pure research looking for the next “ah-ha” discovery.

Another critical R&D issue is the changing innovation pipeline delivered by technology start-ups.  In the past, the industry enjoyed a healthy ecosystem of emerging companies funded by venture capital that were ripe candidates for merger and acquisition.  Today, VC venture funding in the semiconductor industry is down nearly 50 percent from 2009 levels.  To help address this problem, SEMICON West will feature the first Silicon Innovation Forum (SIF) focused on new and emerging companies in the industry.  Organized by Applied Ventures, Dow Chemical Company, Intel Capital, Micron Ventures, TEL Venture Capital, and Samsung Ventures, SIF is designed to bridge funding gaps for new and early-stage companies by providing a platform to showcase new ideas to potential partners and investors.  SIF will consist of an open conference program on July 9 which is free to all SEMICON West attendees, followed by a reception and showcase for qualified investors.

The International Technology Roadmap for Semiconductors (ITRS) has been a critical component in the R&D planning process and SEMICON West will again feature presentations and discussions on the latest version.  The ITRS is undergoing a major change this year to reflect the market evolution towards highly-flexible mobile devices. Presentations include topics on system drivers, design, modeling and simulation, process integration, devices, and structures (PIDS), lithography, front-end processes (FEP), and emerging research devices (ERD). Back-end-of-line working groups will present challenges for future interconnects — such as through silicon vias (TSVs); the latest roadmaps for semiconductor assembly; systems packaging applications, “More than Moore,” and the testing considerations for these quickly changing technologies.  They will also discuss roadmap developments in micro-electro-mechanical systems (MEMS) and radio frequency and analog/mixed-signal technologies (RFAMS).  Look for these report-out sessions on the SEMICON West TechXpots on Thursday, July 11.

Other critical R&D topics that will be discussed at the SEMICON TechXPOT sessions are the latest developments in  lithography, processing requirements for non-planar transistors, 450mm wafer processing, advanced materials, and nano-defect metrology.  Unlike a conference with a variety of academic and special-interest topics, the SEMICON TechXPOT sessions quickly and succinctly provide the latest news and status from leading experts in the field, including “in the know” executives from organizations like ASML, Intel, GF, SEMATECH, G450C, ASE, ST Microelectronics and many more. In addition to their public presentations, TechXPOT speakers often make themselves readily available, providing suppliers and other stakeholders critical information on technology requirements and opportunities.

R&D engineers and scientists remain one of the most important audiences at SEMICON West.  Through private meetings with their top customers and suppliers, and through TechXPOT and other programs that deliver the latest developments in key areas of industry development, we think SEMICON West provides the most cost-effective and time-efficient value in the industry.  I hope you can join us.

For more information on SEMICON West and to register, visit www.semiconwest.org (free registration ends on May 10)

Dynamic changes to R&D processes, tools, technical challenges, and funding/business models will be highlighted at SEMICON West 2013, along with product displays of the latest semiconductor manufacturing technology, components and subsystems. SEMICON West, the Western Hemisphere’s largest micro- and nano-electronics exhibition and conference, will be held July 9-11 at the Moscone Center in San Francisco. The event will feature over 500 exhibitors, 50 hours of conference programs and more than 30,000 industry attendees.  Registration is now open at www.semiconwest.org without charge until May 15; registration fees apply starting May 16.

The semiconductor industry is simultaneously addressing the most complex challenges in its history: EUV lithography, new transistor architectures, stacked 3D-ICs, and 450mm wafer transition.  At the same time, adjacent markets in LED, MEMS and printed/flexible electronics are approaching technology crossroads — and new, post-CMOS alternatives to extend Moore’s Law are in the early stages of development.  Reconciling these multiple R&D demands are transforming old R&D strategies and accelerating new organizational models, skill set requirements, consortia options, partnership strategies, global sourcing tactics, and other approaches to managed innovation.

SEMICON West addresses these new R&D approaches through a variety of keynote presentations, panel discussions, technical presentations, and collaboration sessions including:

  • Silicon Innovation Forum: Organized by the industry’s leading strategic investment groups, this first-time forum provides a platform to connect new and emerging companies with strategic investors, venture capitalists and industry leaders.
  • Consortia Views:  For the first time anywhere, leaders from the industry’s top consortia — SEMATECH, imec and CEA-Leti — will share their views on collaborative R&D and the future of semiconductor technology.
  • Keynote Perspectives:  Ajit Manocha, CEO, GLOBALFOUNDRIES
  • Essential R&D Process Sessions:  Nano-Defect Detection and Lab-to-Fab Solutions
  • Latest Technology Updates:  Industry leaders will share the latest updates on lithography scaling and productivity, processing requirements for nonplanar transistors, 2.5/3D stacked ICs, and 450mm wafer processing.
  • ITRS Public Sessions:  The most critical technology innovation targets as identified the International Technology Roadmap for Semiconductors.
  • New Technology Sessions:  Learn about the latest R&D opportunities and challenges in LEDs, MEMS, printed/flexible electronics, silicon photonics, and more.

SEMICON West is the annual tradeshow for the micro- and nano-electronics manufacturing industries. Last year, over 30,000 attended the event and over 500 companies exhibited the latest innovations and solutions for advanced manufacturing.  For the sixth year, SEMICON West will be co-located with Intersolar North America, the leading solar technology conference and exhibition in the U.S. Every major semiconductor manufacturer, foundry, fabless company, equipment and materials supplier — plus leading companies in LEDs, MEMS, displays, printed/flexible electronics, PV, and other emerging technologies — attend SEMICON West.

SEMI is the global industry association serving the nano- and microelectronics manufacturing supply chains.  SEMI maintains offices in Beijing, Bengaluru, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C.