Category Archives: Wafer Level Packaging

October 14, 2011 — Steven J. Adamson, marketing specialist with dispensing/coating/jetting equipment maker Nordson ASYMTEK, received the Daniel C. Hughes, Jr., Memorial Award, for the greatest contribution to IMAPS and the microelectronics packaging industry, including technical and service contributions.

The International Microelectronics And Packaging Society (IMAPS) is dedicated to the advancement and growth of microelectronics and electronics packaging. Adamson received the award during the IMAPS conference in Long Beach, CA this week.

Adamson chaired the San Diego IMAPS chapter for 2 years, was general chairman of the 2006 International Symposium on Microelectronics, and served as IMAPS president in 2008. In 2009, he volunteered to be chairman of the IMAPS Microelectronic Foundation, which helps students and academia participate in IMAPS activities through grants and awards. In 2010, Adamson received the IMAPS President’s Award.

Adamson accepted the award with an acknowledgement of the importance of IMAPS to students — with funding, paper publicity, event travel — and the importance of students to IMAPS.

Adamson is a 30+ year veteran in microelectronics assembly, working at Nordson ASYMTEK since 1998, as well as time at Kodak, Motorola, PLessey, International Computers Ltd.

Bio:
Adamson has held positions at Nordson Asymtek as applications engineering manager, and marketing specialist. He has worked in all aspects of packaging and assembly from R&D to manufacturing, designing multi-chip modules, hybrid circuits, printed circuit boards, thermal printed heads, and magneto-resistive head assemblies. He has delivered technical papers on wire bond encapsulation, chip scale package and flip chip assembly, PCB design rules, and reliability and has had papers published in leading industry trade journals both domestically and internationally. He is co-author with Charles Harper on a book titled, "Handbook of Plastic Processes," published by McGraw-Hill.

Adamson previously held positions with Kodak, Motorola in the U.S., and Plessey, International Computers Ltd in the U.K.  He has been awarded five US and two UK patents. In 2005 he was presented with an award by the San Diego Engineering Council for "Outstanding Service to Electrical Engineering". Originally from the U.K., he holds a Higher National Certificate in Electrical Engineering from Stockport College of Technology and for several years was the lead instructor and advisor to the University of California San Diego (UCSD) extension course on Microelectronic and Optical Packaging.  

IMAPS leads the microelectronics packaging, interconnect and assembly community, providing means of communicating, educating and interacting at all levels. Find out more at www.imaps.org.

Nordson ASYMTEK makes precision automated fluid dispensing, conformal coating, and jetting technologies. For more information, visit NordsonASYMTEK.com

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October 5, 2011 – BUSINESS WIRE — Analog Devices Inc. (ADI) introduced a packaging technology for digital isolators that achieves a minimum of 8mm creepage distance required by global industry standards to ensure safe operation in high-voltage medical and industrial applications.

Incorporating Analog Devices’ iCoupler digital isolation technology, the package achieves 8.3mm creepage. The new design is Canadian Standards Association certified. It suits advanced medical diagnostic, measurement and monitoring; and industrial and instrumentation systems that operate up to 220-250V AC.

Creepage is the shortest distance over an insulating surface — an IC package in this case — over which an arc may travel between two galvanically isolated conductors. A 220-250V working voltage requires a minimum of 8mm. The JEDEC-standard 16-lead SOIC has 7.6mm of creepage; ADI extended the package length by 2.5mm to enlarge the creepage path, while remaining compatible with JEDEC standard footprint. ADI developed the package to replace lower-performing optocouplers, delivering 4x the data rate and using 90% less power, according to the company.

ADI’s iCoupler technology is based on chip-scale transformers, offering power, stability, and data rate advantages over optocouplers’ LED or photodiode systems. The transformers are planar structures formed from CMOS and gold metal layers, fabricated directly on-chip using wafer-level processing. A high-breakdown thick polyimide layer under the gold insulates the top and bottom transformer coils. CMOS circuits connected to each coil provide the interface between each transformer and its external signals. iCoupler channels can be integrated with each other and other semiconductor functions.

Coupler Digital Isolators Available in 16-Lead Certified SOIC Package
ADuM220x Dual-channel isolators
ADuM221x Dual-channel isolators
ADuM225x Isolators with non-latching bidirectional communication channels
ADuM240x Quad-channel isolators
ADuM4160 USB isolator
ADuM440x Quad-channel isolators
ADuM6000 Isolated dc-to-dc converter*
ADuM620x Dual-channel 5-kV isolators with integrated dc-to-dc converter*
ADuM640x Quad-channel isolators with integrated dc-to-dc converter*
ADM268xE 5-kV rms signal and power isolated RS-485 transceivers*
  *Certificate available in December.

Analog Devices provides data conversion and signal conditioning chips. Analog Devices’ common stock is listed on the New York Stock Exchange under the ticker "ADI" and is included in the S&P 500 Index. To watch a short video on the new iCoupler digital isolator packaging, visit http://www.analog.com/8mmpackaging.

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IMAPS 2011 preview


October 3, 2011

October 3, 2011 — IMAPS 2011, the 44th International Symposium on Microelectronics, will take place October 9-13 at the Long Beach Convention Center in Long Beach, CA. Ahead of the show, here are some of the highlights for attendees.

Take in the exhibits. Exhibit hall passes are free to all IMAPS 2011 attendees. This includes the exhibitor booths and welcome reception, as well as the keynote presentations and the Global Business Council Marketing Forum. Keynotes will be presented by Liam Madden, corporate VP, Xilinx Inc. and Dr. Ning-Cheng Lee, VP, technology, Indium Corporation.

New professional development courses this year cover counterfeit electronics, advanced packaging, and how to design and analyze an experiment.

The nearly 200 papers at IMAPS 2011 will be divided into 6 tracks:

  • 3D Packaging
  • Modeling/Reliability
  • Next Gen. Materials
  • Assembly & Packaging
  • Advanced Technologies
  • Focus Track: Adv. Packaging & System-Integration.

This year, the GBC forum is titled "Tomorrow’s Supply Chain: Overcoming Environmental & Societal Challenges." In the forum, IBM will look at how packaging is changing the data center, Medtronic will look at the impact of rework, and Hewlett-Packard (HP) will examine the electronics industry’s social and environmental roles.

Learn more before the show by visiting www.imaps2011.org.

IMAPS 2011 news:

Palomar Technologies to discuss pulsed heat eutectic solder and chain wire bonding for HB-LEDs

ALLVIA to present latest data for silicon interposers and embedded capacitors

 

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September 30, 2011 — Toshiba Corporation (TOKYO:6502.t) signed a non-binding memorandum of understanding for Amkor Technology, Inc. (Nasdaq:AMKR) to acquire Toshiba Electronics Malaysia Sdn. Bhd. (TEM), which is a semiconductor assembly operation in Malaysia. Amkor will also have the right to license certain related intellectual property rights.

TEM performs assembly and test of discrete and analog semiconductors, with a main focus on power semiconductors in recent years. The facility opened in 1973.

Toshiba sees power semiconductors as a growth driver for its business. Transferring TEM ownership to Amkor will bring TEM into a large-scale network of packaging/materials procurement capabilities. Toshiba will subcontract power semiconductor assembly and test to TEM. The TEM operations will become more efficient and Toshiba will benefit with a better back-end cost structure for power semiconductor assembly, the companies report.

Toshiba plans to focus its resources on front-end wafer fabrication for power semiconductors, reinforcing production at Kaga Toshiba Electronics Corporation in Japan

September 27, 2011 – Marketwire — Cascade Microtech Inc. (NASDAQ:CSCD) completed the sale of its test socket manufacturing business for a purchase price of $550,000 to R&D Interconnect Solutions, a wholly owned subsidiary of R&D Circuits, based in Brooklyn Park, MN.

Cascade’s board of directors also authorized a stock repurchase program under which up to $2,000,000 of its common stock may be repurchased. Shares may be purchased from time-to-time in the open market or in privately negotiated transactions. The timing and actual number of shares purchased will depend on a variety of factors, including market conditions, corporate and regulatory requirements, and alternative business and investment opportunities. Repurchases under the program will be funded from available cash. The program does not require the Company to acquire any particular amount of common stock, and the program may be commenced, suspended or terminated at any time or from time-to-time at the Company’s discretion without prior notice.

Cascade Microtech will not purchase any stock under the repurchase program until it announces its financial results for its third quarter on November 1, 2011.

The sale of CSCD’s test socket business, and this share repurchase program, will help bring Cascade Microtech’s stock value up and build long-term value for shareholders, said Michael Burger, president and CEO.

Cascade Microtech Inc. (NASDAQ:CSCD) makes precision contact, electrical measurement and test products for integrated circuits (ICs), optical devices, etc. For more information, visit www.cascademicrotech.com.

R&D Interconnect Solutions specializes in design and production of high-performing sockets and interconnect products for testing of packaged ICs. It is wholly owned by R&D Circuits. For more information on R&D Circuits, visit www.rdcircuits.com.

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September 26, 2011 – Earlier this month, Invensas Corp., a wholly-owned subsidiary of Tessera Technologies (Nasdaq: TSRA) demonstrated the dual-face down (DFD) implementation of its new multi-die face-down (xFD) packaging technology at the Intel Developer’s Forum (IDF, San Francisco, CA). The new technology targets the increased DRAM capacity and performance now needed by data centers because of rapid growth in multi-core processing and computing virtualization. The company is also targeting notebook computers, tablets and smart phones that need better battery life with a reduced form-factor.

Simon McElrea, president of Invensas, spoke with SST in a podcast interview about the wire bond-based packaging technology that mounts integrated circuits (ICs) upside down and staggers them in a "shingle-like" configuration, so the wire bonds poke through the bottom of the substrate. This gives an electrical advantage: "Because we remove spacers and face-up wire bonds, you get a super thin package that aids in heat transfer," he said. "And because you’ve staggered the die, you get heat transfer through the bottom chip as well as the top chip, without having to take all the heat through the die stack." The company says that heat transfer in the DFD package is improved 20%-30% in comparison to conventional dual-die packages (DDPs).

The company reports that the new packaging decreases the overall component size with a 25%-35% savings in vertical height over conventional solutions, and enhances electrical performance with a 50%-70% improvement in speed-bin yield (Figure 1). "This is based on data from thousands of parts," McElrea told SST. Keeping both die with very short interconnects results in the equivalent of single-die performance, though there are multiple die in the package: "Instead of dumbing down the performance of the multi-chip package to your slowest chip — the top chip — you get the performance of the silicon itself," he said.



Figure 1: Sort yield advantage comparing DFD packaging vs. conventional DDP packaging. (Source: Invensas)

McElrea explained that xFD technology costs less to manufacture than conventional multi-die DRAM packages because it uses a parallel process flow — i.e., all the chips are stacked at the same time in one station, and then all the die are wire-bonded at the next station, so all of the pads are exposed in the stacking structure. Cost reductions also come from a significant reduction in gold and other material usage. Furthermore, the package is manufactured on existing wire bond assembly lines (Figure 2).



Figure 2: Dual-die DRAM package structure comparison. (Source: Invensas)

September 23, 2011 — Research and Markets released "Wafer Packaging Fab Database," providing a global overview over 150 companies’ 250+ mid-end semiconductor packaging houses. Small R&D and prototype lines are also listed. Data includes wafer-level packaging (WLP) activity and installed capacities.

Flip chip wafer bumping and wafer-level chipscale packaging (WLCSP) make up the mainstream of WLP. On the leading edge are through silicon via (TSV) for 3D WLP, 2.5D interposers, fan-out WLP (FOWLP) and other technologies that require new capacities and capabilities.   

The database references more than 250 fab locations worldwide with technical information on wafer bumping, re-distributed layers (RDL), passivation, through-silicon via (TSV), and "mid-end" capabilities, and wafer-level packaing capabilities in general.

The database targets equipment & material suppliers looking for customer opportunities, fabless/fab-lite semiconductor companies looking to outsource, and other users.

WLP technologies distribution can be sorted by players, technology type, country, business model, investment & growth evaluation. Users can view the companies performing a certain packaging technology, and study players manufacturing/outsourcing strategy and supply chain. Others can identify and source new WLP service suppliers for their wafer-scale packaging needs. 20+ graphs are included to illustrate global trends.

Sample of companies listed in the database (IDMs, OSAT, foundries, MEMS, R&D Lab, etc.)
Wafer bumping houses:   
NEPES  

ChipBond  

FCI

 OSAT:   
ASE   

SPIL   

STATS ChipPac  

Wafer packaging houses:   
Xintec  

China WLCSP   

Nemotek  

OptoPac

 R&D Lab & prototype lines:   
CEA LETI  

IMEC  

RTI

MEMS IDM/foundries:   Silex  

Dalsa   

APM

 TSV foundries:   
ALLVia  

EPWorks 

 IC manufacturers (IDM):   
Texas Instruments  

STMicroelectronics 

Samsung 

 CMOS foundries:   
TSMC   

Globalfoundries   
UMC

For more information, visit
http://www.researchandmarkets.com/product/5def06/wafer_packaging_fab_database

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September 22, 2011 — X-RAY WorX GmbH introduced electronically controlled venting valves for open X-ray tubes. This avoids the manual venting typically performed during X-ray tool maintenance. The new venting method considers the turbo pump’s rotation speed and automatically optimizes tube venting.

X-RAY Worx asserts that the automatic venting process protects the turbo pump from damage and reduces downtime for X-ray system maintenance.

The company is also introducing 240kV microfocus X-ray tubes, the XWT-series with 240kV acceleration voltage, for computed tomography (CT) systems and penetration of higher wall-thicknesses in two- and three-dimensional X-ray analysis.

The high voltage technology used for the new 240kV X-ray tubes has been certified by the original supplier. The acceleration voltage of 240kV is available for almost all types of microfocus X-ray tubes of the XWT-series offered by X-RAY WorX.

X-RAY WorX makes microfocus X-ray tubes for high-resolution X-ray analysis of electronics, aerospace and automotive products. X-RAY WorX supports users of microfocus X-ray systems with a broad range of services ranging from preventive maintenance and repair to the supply of spare parts and trainings. Go to www.x-ray-worx.com

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September 20, 2011 — The first annual Global Interposer Technology Workshop (GIT 2011) will take place November 14-15 at Georgia Institute of Technology (GA Tech), convening industry experts, global academic researchers, and student leaders to share interposer technology research, development, applications, markets and manufacturing infrastructure.

Interposers are used to create "More than Moore" 3D or 2.5D semiconductor packaging.

To present at the conference, submit a title for consideration (presentation or poster) by October 2 at http://www.prc.gatech.edu/git2011/papers.html. Selected submitters will be notified by October 15.

Technical sessions will cover electrical and mechanical design, silicon and glass interposers, chip- and board-level interconnect, interposer applications and markets, and the manufacturing infrastructure for these technologies.

The plenary keynote lineup is as follows:

  • Subramanian Iyer, IBM – "Silicon Inteposers: The First Step Towards Three Dimensional Integration"
  • Doug C.H. Yu, TSMC – "Semiconductor Paradigm Shift and the Advantages of Foundry Integration"
  • Suresh Ramalingam, Xilinx – "Stacked Silicon Intereconnet: Road to Production"
  • Jerome Baron, Yole – "Interposer markets and Applications"
  • Rao Tummala, Georgia Tech – "3D Packaging Perspective at Georgia Tech 3D ICs vs 3D Interposer"

The event will feature posters presented by students along with the industry, research, and academia speakers.

GIT 2011 is sponsored by IEEE, CPMT, IMAP, iNEMI, and SEMI. Learn more at www.prc.gatech.edu/git2011.

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