In 2006 while the industry was deep in the R and D phase of 3D IC technology, I wrote a piece concerning “posturing and positioning” as the first phase of 3D IC technology commercialization [ “Posturing and Positioning in 3-D IC’s”, Semiconductor Int. April 2007]. The premise was that the 3D IC announcements at the time by Intel, IBM, Samsung, NEC, Elpida were the beginning of commercialization, stage (1) or “the bragging stage” if you will, where technology companies like peacocks strut around showing their feathers and announcing “we are the best”.
Stage (2) “real commercialization” came in 2010 when Elpida/UMC [see IFTLE 8, “3D Announcements and Rumors”]and Samsung [see IFTLE 27, “The Era of 3D IC Has Arrived with Samsung Commercial Announcement” ] announced 3D IC based memory products (albeit for late 2011- 2012). The expectation is that this will cause further announcements from competitor companies attempting to keep up in the technology race , a pattern we saw recently in the introduction of TSV technology for CMOS image sensors [see PFTLE 46,“…..on Mechanical Bulls, Rollercoasters and CIS with TSV” ].
Stage (3) I would define as the period where standardization begins to occur, the infrastructure begins to “gel” and technology ownership begins to clarify. For multilayered, complex technologies like 3D IC technology ownership is usually determined in the courts. Dec 6th 2010 is the date that initiated the technology ownership determination for “oxide bonding” technology. This is when Ziptronix filed a complaint against TSMC and Omnivision in Federal Court alleging “willful and deliberate” infringement of several patents [ USP’s: 7,387,944; 7,335,572; 7,553,744; 7,037,755; 6,864,585; 7,807,549; ] owned by Ziptronix pertaining to low temperature oxide bonding. The original SST article can be found here [link]. In question here is the use of oxide bonding for backside illumination in CMOS image sensors [see PFTLE 40, “Backside Illumination (BSI) Architecture next for Next Generation CMOS Image Sensors”]
Most of the CIS manufacturers have moved to BIS technology per a recent market study by Yole Developpment [ see “ CMOS Image Sensors Technologies and Markets -2010”].
Instead of illuminating a CMOS image sensor from the top side (front) of the die, backside illumination (BSI) collects photons from the backside so the light enters the device unobstructed by the metal and dielectric layers of the interconnect structure as shown in the figure.
Cell phone camera image sensor suppliers Omnivision, Aptina Imaging, Toshiba, Samsung and STMicro also appear ready for BSI products to appear in early 2011. Yole expects BSI technology to be responsible for a little over $1B (~17% of CIS sales) in 2012.
TSMC has presented their latest BSI technology in the paper "A Leading-Edge 0.9μm Pixel CMOS Image Sensor Technology with Backside Illumination:Future Challenges for Pixel Scaling" at the 2010 IEDM. They describe the "device wafer runs through a planarization process and is bonded with a carrier wafer. The bonded wafer is then mechanically and chemically thinned down from the bottom side of the device wafer to the target thickness". The process in question is the wafer bonding process. The qustion raised by this complaint centers around whether the accused are using oxide wafer bonding for their OmniBSI® technology, if so, whether the the oxide surfaces are treated with plasma or other chemicals and whether the Ziptronix claims in their numerous patents on the topic are indeed valid. TSMC and its subsidaries Xintec and VisEra appear ready to deliver CMOS image sensor devices to Omnivision.
Chipworks has done reverse engineering on Omnivision products such as the OmniVision OV5642 1.4 μm, back side illuminated (BSI) 5 Mp CIS [link] and teardowns of communication devices such as the HTC EVO 4G Smart Phone which they found contained the OmniVision OV8812 8 Mp Image Sensor chip (below).
BSI technology requires a solution for handling thinned wafers. A typical solution is to direct oxide bond the sensor wafer front surface to another oxide coated wafer which can then serve as a permanent “handle wafer” for the thinning operation.
Direct oxide bonding processes require extremely smooth (0.5 nm RMS) and clean surfaces which are readily achieved with standard CMP. When such SiO2 surfaces are placed into contact, they initially form relatively weak “van-der-Waals” bonds. Subsequent heating to elevated temperatures is necessary to achieve high bond strength through the formation of covalent Si-O-Si bonds. The high thermal budget required for this condensation reaction to proceed ( typically greater than 800 C) is not suitable for most devices, however, modifying the surface chemistry allows the formation of chemical bonds at significantly lower temperatures.
Recent reports from EVG indicate that oxide bonding currently has 35% better placement accuracy and better throughput than polymer bonding as shown in Table [ see PFTLE 41, “3D Integration Stays HOT at Semicon West”]
Using oxide bonding for the “back-end, bonding to carrier step” would result in low temp, high throughput bonding would result in excellent CTE match and positional accuracy.
Ziptronix technology for BSI is centered around ZiBondâ??¢ which they claim allows one to achieve significantly higher bond energy between wafers after treatment with various surface “activating and terminating” processes. The direct oxide bonding, which is initiated at low temperature, is characterized by a very high bond energy between the surfaces. One example of Zibondâ??¢ simply requires a plasma treatment followed by an aqueous ammonium hydroxide rinse. By such surface treatments bond energies in excess of 1 J/m2 are reported.
Next week we will continue our look at presentations from the IEEE 3DIC in Munich.
For all the latest on 3D IC technology and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦..
