By Dr. Phil Garrou, Contributing Editor

For about a decade now, we have been awaiting the full commercialization of 3DIC. From the beginning most practitioners laid out a roadmap where CMOS Image sensors led the way followed by memory stacks, memory-on-logic, logic on logic and lastly the holy grail of heterogeneous integration where we could combine advanced semiconductor materials and different  functions, with high-density silicon CMOS technology.

Indeed CMOS image sensors have led the way [ see IFTLE 199,  “Omnivision Roadmaps 3D stacking for CMOS Image Sensors…” ] and DRAM memory stacks from Hynix and Micron are on the verge of full commercialization [ see IFTLE 202, “ConFab 2014: Novati, Lumileds; Chipworks; IEEE CPMT Packaging Panel”].

A lesser publicized fact is that we are actually very close to functional heterogeneous integration thanks to the efforts of many participants in the DARPA sponsored COSMOS and DAHI programs.

The development of non SI based semiconductor (compound semiconductors, CS) electronics has been motivated by their superior materials properties relative to silicon. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with f_max above 1THz. The wide energy bandgap of GaN has enabled large voltage swings as well as high breakdown voltage RF power devices and the excellent thermal conductivity of SiC makes tens of kilowatt-level power switches possible [1]

[1] S. Raman, “The DARPA Diverse Accessible Heterogeneous Integration (DAHI) Program: Towards a Next-Generation Technology Platform for High-Performance Microsystems”, 2012 CS Mantech Conf.

DARPA proposes  that the future of CS electronics depends not on displacing Si, but rather on heterogeneous integration of compound semiconductors with silicon technology in a way that will take advantages of the two technologies when combined.

Past attempts at heterogeneous integration has been at the module level, i.e Multichip Modules [see “Multichip Module Technology Handbook” , P. Garrou, I Turlik Eds., McGraw Hill, 1998].

However, MCM techniques have been limited by I/O parasitic effects between chips in such modules and by device and interconnect variability issues. Many of the limitations including I/O parasitics and phase mismatch are governed by the length of separation between CS and Si CMOS devices, and as such, reduction of this separation is expected to yield dramatic improvements in performance of heterogeneous integrated circuits.

The COSMOS [ Compound Semiconductor Materials on Silicon] program began in 2007 with teams led by Northrup Grumman, Raytheon and HRL (Hughes Research Labs).  They have demonstrated three different approaches (see below) to achieving InP BiCMOS integrated circuit technology featuring InP HBTs and deep submicron Si CMOS for RF and mixed signal circuits.

The Northrop Grumman technology starts with a completely fabricated standard CMOS wafer. A separately fabricated InP HBT wafer (thinned to approximately 55u m) is mounted to a glass carrier. An InP wafer is etched to form individual chiplets (still attached to the carrier wafer). The CMOS wafer is prepared for integration with the InP chiplets by depositing gold (Au) micro bumps (3-10um and 2um thick). The glass carrier containing the singulated InP chiplets is then aligned to the CMOS wafer, and the bonding operation performed using standard wafer bonding equipment with controlled time, temperature, and bonding force. The glass carrier wafer is then released, leaving the singulated InP chiplets connected to the base CMOS wafer. This is shown schematically below.

DARPA is also pursuing the integration of GaN transistors with Si CMOS on a Si substrate.  For example. the Raytheon team has recently demonstrated a monolithically integrated RF amplifier circuit  using heterogeneously interconnected GaN HEMTs and pMOS gate bias control (see below).

DAHI (Diverse Accessible Heterogeneous Integration)  initiated in 2013 is based on its predecessor COSMOS and is composed of several design, technology and manufacturing thrusts including :

• Si CMOS for highly integrated analog and digital circuits
• GaN for high-power/high-voltage swing and low-noise amplifiers
• GaAs and InP HBT and HEMT for high speed/low-noise circuits
• Compound semiconductor optoelectronic devices for direct-bandgap photonic sources and detectors, as well as or silicon-based structures for modulators, waveguides, etc.
• MEMS components for sensors, actuators and RF resonators
• Thermal management structures

Program teams include:

• Teledyne/Tezzaron/UC Santa Barbara
• MIT/Raytheon/Stanford
• IBM/Columbia U/MIT/Veeco
• NG/Novati/Nuvotronics/MOSIS/ON Semi
• HRL/ UC San Diego/U Mass/U FLA
• Raytheon/Novati/IBM
• Rockwell/Tower Jazz/UCSD

At the recent DAHI program review in Boulder participants shared their technology progress to fabricate multilayer circuit structures (i.e InP, Si, GaN) on substrates such as SiC using 3DIC technologies such as TSV and oxide-oxide bonding.

The  goal of DAHI is to establish a manufacturable, accessible foundry technology for the monolithic heterogeneous co-integration of diverse (e.g., electronic, photonic, MEMS) devices, and complex silicon-enabled architectures, on a common substrate platform for defense and commercial users. By enabling the ability to ‘mix and match’ a wide variety of devices and materials on a common silicon substrate, circuit designers can select the best device for each function within their designs.  This integration would provide DoD systems with the benefits of a variety of devices and materials integrated in close proximity on a single chip, minimizing the performance limitations caused by physical separation among devices.

As these technologies become public, IFTLE will keep its readers apprised of the results.

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