IDCs: A Socketless Test Solution
10/01/2005
A STRESS-HARDWARE CONCEPT
BY CARLO GRILLETTO
Plastic ball grid arrays (BGAs) are becoming more sophisticated, with decreased pitch geometries and increased ball quantities. The advent of 3,000-ball BGAs represents the next step. New building materials and geometries are being investigated and evaluated. This creates a challenge for reliability stress testing and designing the necessary supporting hardware.
For the purpose of IC package reliability stress testing we use both a product qualification (PQ) chip with specialized active circuitry or a silicon design that contains metallization routing to bridge two package substrate traces, creating a simple electrical “loop” between two BGA balls. This is called a Modified Daisy Chain.1 The loop electrical path contains the substrate trace and vias, the substrate-to-die connection (whether wire bond or flip chip), and the intra-die connections to the die trace in a series. These loops are placed geometrically so adjacent substrate features can be set at opposing electrical bias during stress testing.
This article deals with a new concept in stress hardware that can be designed and manufactured easily, and reduces development time and stress test costs. It has been adapted successfully for bias/humidity/temperature (BHT), or highly accelerated stress testing (HAST).
BHT Testing
The most expensive and involved package reliability stress test is the standard BHT, commonly referred to as “85/85”, or HAST. The standard BHT test consists of an electrical bias that is 110% of the maximum device family bias, and 85% relative humidity (RH) at 85°C. The HAST tests consist of the same BHT bias voltage, but is performed at either 110ºC or 130°C, and at 85% RH. The stresses are designed to test for electrochemical corrosion and ion migration that can result in halo and/or dendritic leakage.
To perform a BHT or HAST test, packages must be placed into a separate device, called a stress socket, which makes external electrical connections with the package. For example, these connections will be described in terms of BGAs. The stress socket includes a lid that clamps down on the BGA package, applying pressure. Stress sockets containing the packages are then attached to a board, and the board is placed into a HAST-test chamber. After BHT testing, the packages are removed from the stress sockets and placed into another test apparatus for automated electrical testing (ATE). The ATE tester requires using a different socket to form an electrical connection with the packages.
This method of performing BHT testing works for its intended purpose, but has several disadvantages. First, stress sockets are expensive because they must be custom-made. IC packages come in a variety of shapes and sizes. For example, a BGA package may have 200 to 3,000 balls. Therefore, custom stress sockets must be designed and manufactured for each type of package under test, which is time consuming and expensive. The materials required to build stress sockets add to the cost, as the sockets themselves must be capable of withstanding thousands of hours of BHT conditions.
The second disadvantage is that the test causes stress not only on the packaged device, but also on the test hardware, which requires periodic maintenance. This limits the useful life of the assembled board to approximately 3,000 hours of the 130°C HAST test. The 2.2 atmospheres of superheated humidity, coupled with electrical bias, cause physical and chemical degradation of the board and sockets.
A third disadvantage of socketed BHT testing deals with the boards. Because the sockets are custom-designed, boards must also be custom-designed. These boards can be expensive, especially because they must also withstand harsh test conditions. A minimum of 45 packages are needed for qualification testing, which requires a significant number of boards to mount the sockets.
A final disadvantage of using sockets is their relatively large size. Because of this, the number of sockets that can be mounted on one board is limited, thus limiting the number of packages that can be placed into the BHT chamber at any time. This particularly impacts HAST testing because of the limited chamber size and the large, robust hardware needed.
Interposer Daughtercard Concept
In this methodology, BGA and other surface mounted devices are attached to inexpensive disposable daughtercards (IDC).* The BGAs are both stressed and electrically tested in this mounted state. The need for sockets and device-specific custom boards have been eliminated using this process. Figure 1 shows an initial IDC design with edge-card connectors on both ends for a 313-ball BGA. Figure 2 shows an IDC assembled with a 1,069 1.0 mm pitch BGA device, utilizing the current design with all 62 edge card connectors on one end, and placed on the universal stress board.
 Figure 1. IDC ball-attach pads. |
The IDC scheme includes pads for mounting the I/Os of a test package, edge-card connectors for connecting the interposer card directly to a universal stress board and for performing bias testing on the test package, and pads replicating the test package I/Os for connecting the interposer card to an ATE.
 Figure 2. 1,069 BGA assembled to an IDC and placed in a mother stress board (left). Top view of the same 1,069 BGA (right). |
In stress, the IDC is mounted to a universal stress board (USB) containing multiple pairs of adjustable female connectors for contacting the interposer cards via edge-card connectors. For the IDC design with edge-card connectors on both sides, the connectors are adjustable. The USB can accommodate different sizes of interposer cards, eliminating the need for custom boards. Interposer cards also can be mounted on both top and bottom of the USB, thereby increasing the number of interposer cards that can be placed into a HAST chamber. In the latest single edge-card design, all IDCs are attached to a USB in a vertical position. Figure 4 shows the 27-position 1,069-BGA USB. Using the IDC concept, one can increase the number of devices in a HAST test chamber from two to three times that of a socketed design.
 Figure 3. 313-ball BGA with a 36 edge-card IDC universal motherboard with 50 IDC positions. |
null
 Figure 4. 1,069 BGA with a 62 edge-card IDC universal motherboard with 27 IDC positions. |
The cost of designing and manufacturing the interposer card is a fraction of that of the conventional socketed methods, and the savings may increase as higher ball-count packages and stress boards are developed. The design of the interposer card also reduces design/manufacture lead time (4 to 5 weeks), eliminating board/socket maintenance and storage.
Electrical Circuit
The IDC contains the necessary circuitry to test and stress the packages:
Stress circuitry. Stressing is accomplished by biasing adjacent “loops” oposite each other and the various package Vdd and Vss planes. This is achieved by connecting one end of the loop to a buss bar that is then properly biased by connection to the edge-card connector. Connection from the BGA ball to the buss bar is achieved through the IDC ball-attach pad, then through the IDC via the appropriate bias connect layer, and finally trace-routed to the buss bar. The Vss and Vdd planes are connected similarly.
IDC edge-card connectors are then connected to the USB via edge-card connectors. In the 313-ball IDC, the Vss and Vdd loops are separated and ganged into four individual Vss and four Vdd buss bars, which are clamped to corresponding edge-card connectors. The Vss and Vdd planes have four edge-card connectors each. The 1,069-ball IDC has a similar connection scheme; however, all 32 top edge-card connectors are connected to Vdd, while all of the bottom 32 are connected to Vss. This assures maximum Vss-to-Vdd distance separation.
Test Circuitry. Each of the package BGA balls have vias that connect directly to an exact replica-pad layout on the bottom of the IDC. Connection to the ATE device-under-test (DUT) board is accomplished through a test socket that connects the bottom-side pads of the IDC to lands rather than balls.
Electrical Testing
An ATE system in a standard fashion achieves continuity testing, with the IDC functioning as an interposer between the package and the DUT-board socket. This is possible electrically because only one side of the package die “loop” is attached to the buss bar. Leakage or shorting between loops or across package keep-out rings is accomplished in sequential steps:
- Test each of the edge-card connectors to determine if any Vdd-to-Vss leakage exists by handheld meter, a simple data logger setup, or by ATE testing.
- If a cumulative leak is detected, then the IDC is cut at the dotted line to isolate to a specific loop. This removes the buss bar and isolates individual loops. IDC cutting is accomplished by using of a laboratory sample-cutting wheel.
- Leak testing is performed with the ATE in a standard fashion.
USB Design
The USB comprises a simple 2-layer board manufactured to the same standards as conventional stress boards. They can be interchanged in the BHT or HAST chamber by plugging into the backplane cage assembly. IDC edge-card connections are made by incorporating female edge-card connectors that are on the USB.
Manufacture and Assembly
Currently, USBs and the IDCs are being manufactured and assembled by a commercial board and assembly supplier.2 The IDCs are manufactured to the same standards as the conventional HAST test boards, which have demonstrated high reliability. Assembly of the packages to the IDC is accomplished with standard board-assembly procedures. The only difference is that the assembled units were washed three times, rather than the suggested single wash. This was done to ensure that flux residue is kept to a minimum. Disassembly showed no visual flux residue present between the package and IDC.
Ten samples of a 313-ball BGA were used for the test. The samples were chosen from a lot of suspicious quality. The samples were preconditioned by moisture, loaded to a JEDEC Level 3, and subjected to 3× reflows, the last reflow being assembly to the IDC. The samples were mounted to two USBs and subjected to 100 hours of 130°C/85% RH HAST.
ATE testing is performed with a standard DUT board, but modified to include a socket that used alignment pins for IDC placement. This allows the same socket to accept IDCs both with and without the buss bars removed. Final testing showed no leakage; however, two loops on one sample indicated an open circuit. All 10 samples had the buss bars removed by cutting to determine if this procedure would produce a short - none of them did. Failure analysis was performed on the two open loops. The analysis showed both loops, which were positively biased during HAST, demonstrated bond-pad corrosion and lifted ball bonds. Dark field examination of the traces also indicated that the four traces were biased properly. As expected, all the positive-biased traces showed some level of discoloration.
Failure Analysis
Failure analysis is performed in the following manner:
- Bench verification is performed at the IDC underside pads with an ohmmeter. If the failure is a short, then the buss bars are cut off.
- Underfill the package to IDC area (optional). This may not be necessary, but if there is any concern that this may disrupt the second-level connections, then heat the package to ~80°C, syringe-apply the underfill, and cure at a low temperature of ~110°C. If underfill is used, then it should be applied before cutting off the buss bars (for shorts).
- Grind off the IDC to the reverse side of the IDC ball bond pad (or connecting metal and re-probe).
- Grind to the BGA ball.
- Proceed with FA in the standard manner for a BGA.
Conclusion
An effective method has been developed for BHT, including HAST bias testing of complex IC packaging designs at a relatively reduced cost compared to conventional hardware. The designs for different package layouts are accomplished using minimum engineering design effort, and the hardware can be designed and manufactured in about one month. Stress testing is accomplished with the device in the same surface mount configuration as the actual field use. Any contributions of the board-attach process are included in the test. Testing on standard BGA packages demonstrated that the method worked successfully for detecting a corrosion-induced problem. Current package designs in the range of 2,500-ball BGAs can be accommodated easily with a 12-layer IDC. This includes ATE measurement and BGA-attach pads. We are currently developing this method to perform second-level thermal cycle reliability evaluation.
* LSI Logic, Inc. Milpitas, CA.
References
- Grilletto, et al., internal paper submitted to publication, “Modified Daisy Chain Test Chip.”
- Pycon Inc., Santa Clara, CA.
CARLO GRILLETTO, project manager, corporate reliability, may be contacted at LSI Logic Inc., 1621 Barber Lane, Milpitas, CA 95035; 408/433-8362; e-mail: [email protected].