Underfill Effects on BGA Drop, Bend, and Thermal Cycle Tests
02/01/2005
SIGNIFICANT PERFORMANCE IMPROVEMENTS
BY EDWARD IBE, KARL LOH, JING-EN LUAN, AND TONG YAN TEE
Underfill typically is not used to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) at the board level. However, the use for fine-pitch BGAs and CSPs in handheld devices, such as cell phones and PDAs, in automotive electronics, and in military applications, is increasing as the need for greater miniaturization and higher performance grows. In these applications, mechanical stresses can induce early failures. This article presents data showing the effects of BGA underfill encapsulation on solder joint performance under drop and bend tests, and thermal cycling. Relative solder joint reliability and failure modes are analyzed.
Board-level Testing
The test vehicle is a 2 × 5-mm array of 10 daisy chain BGAs, as shown in Figure 1. The 0.5-mm-pitch BGA, with 7 × 7-mm package size, 4 × 4-mm die size, and 84 solder balls, is shown in Figure 2. The BGA was underfilled with a commercially available product.* Thermomechanical properties of the materials used in the test vehicle are illustrated in Table 1.
 Figure 1. Package position on test board. |
Drop Test. For the drop test, the test vehicle was mated to a fixture and drop block with screws. The block was dropped from a height of 1.4 m along two guiding rods, onto a surface covered with a layer of felt. The board was tested until all components failed, or up to the maximum number of 250 drops. Impact acceleration was measured at the PCB mounting screw, with an acceleration of 3,700 G (1 G = 9.81 m/s2) and impact duration of 0.4 ms. A single test vehicle per case was tested, with and without underfill. Consistent results with high repeatability were demonstrated on the tester.
 Table 1. Thermomechanical material properties. |
Bend Test. A board-level bend test was carried out using a tester.** The board with components facing down was placed on two supports with a span of 105 mm, and a cyclic load acted upon the board center with downward displacement of 4 mm (speed of 400 mm/min.). One test vehicle per case was tested, with and without underfill.
 Figure 2. Schematic of BGA CSPs. |
Thermal Cycling. The boards were placed in a thermal cycle, with a test condition of -40° to 125°C at 40 min./cycle. An event detector was connected to the system to measure real-time solder joint failure. Three test vehicles were tested per case, with and without underfill.
Experimental Results
Experimental results for the drop and bend tests, and thermal cycling are shown in Table 2.
 Table 2. Drop test, bend test, and thermal cycle test results. |
Drop Test. For the drop test, solder joint failures are induced by shock and board bending. Therefore, components at the board center (E and F) are more likely to fail, since the board center has the maximum bending. Components away from the board’s center (A, B, C, D, G, H, and I) can withstand a greater number of drops before failure. Component J may have assembly defects, resulting in a low number of drops to failure. In subsequent drop tests at a different height (unreported here), component J was never the first failure and its impact life was much longer than that of components at the board’s center. The board length (115 mm) is larger than its width (77 mm), according to Zones 1, 2, and 3, so packages fail along the board length. Components located in the same zone fail around the same time.
In Zone 1, components without underfill fail after about 30 drops. With underfill, drop test performance is possibly improved, but without statistical significance. In Zones 2 and 3, components without underfill require more than 50 drops to induce failure. With underfill, drop test performance improves significantly.
Bend Test. Component position is a significant factor, because solder joint failures are induced by board bending, though at a lower strain rate than in the drop test. Components at the board center are more susceptible to failure than those farther from the center. Components near the edge can withstand a large number of bending cycles without failure.
In Zone 1, components without underfill fail after 900 cycles. With underfill, performance is possibly improved, but without statistical significance. In Zone 2, components without underfill fail in thousands of cycles. Those with underfill fail in tens of thousands of cycles - a dramatic improvement. In Zone 3, testing without underfill stopped at 50,000 cycles, and testing with underfill stopped at 200,000 cycles - both without failures. Thus, no direct comparison can be made.
Thermal Cycling. For thermal cycling, component position is insignificant. Components fail randomly at any position on the board. Solder joint failures are induced by CTE mismatch among solder joints, package, and board during thermal cycling. The failure mechanism is different than both drop and bend tests.
 Table 3. Temperature cycle performance. |
First failure and characteristic life are shown (to 63.2% failure rate) ain Table 3. The results are based on data collected from 30 packages. Without underfill, the first failure is 358 cycles and characteristic life is 556 cycles. With underfill, the results are 2,254 cycles and 11,001 cycles, respectively.
Failure Analysis
Dye penetration test and cross sectioning of solder joints were performed for the drop, bend, and thermal cycling tests to determine failure locations, interfaces, and modes. In the dye penetration test, a red dye that diffuses into any solder joint cracks was injected into a test sample. After dye and pry, solder joints show shiny facture surfaces, while failed solder joints are stained with red dye. A combination of dye penetration test and cross section techniques provide a full picture of solder joint failures.
The differences in failure modes are caused by unique loading and failure mechanisms of each board-level test. For drop and bend tests, solder joint failures were primarily induced by board bending. For thermal cycling, the failures are mainly a result of CTE mismatch of packaging materials during temperature changes. Therefore, in drop and bend tests, critical solder joints mainly fail in peeling mode during board bending. While in thermal cycling, solder joints usually fail in shearing mode.
 Figure 3. Failure analysis of the drop test. |
Drop Test. For the drop test, solder joints fail at the outermost row along the board’s length (Figure 3). The first solder joint failure occurred at the corner solder ball, cracking along the solder/component pad interface. Failures of several non-critical solder joints were observed along the solder/board pad interface. Distance-to-neutral point (DNP) effect is dominant for both drop and bend tests, because the board bends and induces high tensile stress to the solder joints. After the drop test, the solder joint was observed to have a smooth fracture surface. This is a brittle type of failure, usually induced by stress-controlled, high cycle fatigue. Solder joint peeling stress, therefore, can be used as the failure criteria in the drop test simulation.
 Figure 4. Failure analysis of the bend test. |
Bend Test. For the bend test, solder joints also fail at the outermost row along the board’s length (Figure 4). The first solder joint failure occurred at the corner solder ball, cracking along the solder/component pad interface. Failures of several non-critical solder joints were observed along the solder/board pad interface. The DNP effect was dominant for drop and bend tests, because the board bends and induces high tensile stress to solder joints. A dimpled solder joint failure interface was observed.
 Figure 5. Failure analysis of the thermal cycling test. |
Thermal Cycling. For thermal cycling, solder balls under the die edge are more likely to fail (Figure 5). The local CTE mismatch between die and solder balls has a more significant effect that DNP on solder joint failures that are along the solder/component interface. Just as for the bend test, thermal cycling generated a dimpled solder joint failure interface.
Effect of Board-level Underfill
As the drop and bend tests’ data from Zones 2 and 3 show, underfill can significantly affect performance. However, as seen in Zone 1, there is a critical stress at which the use of underfill yields little or no benefit.
Figure 6 shows the mean impact life of a drop test correlated to the maximum normal peeling stress of a solder joint obtained from modeling. An impact life prediction model was formulated using the Power Law approach to relate the maximum peeling stress of critical solder joints and the mean impact of life:
N50 = C1σzC2, where N50 is the mean impact of life (number of drops to failure at 50% failure rate); σz is the maximum peeling stress (MPa) in the critical solder ball; and C1 and C2 are the correlation constants, 174052 and -1.328, respectively. Similar life prediction models can be formulated for bend and thermal cycling tests using modified Darveaux’s method (Figure 5).
 Figure 6. Impact life prediction model for CSP. |
Using underfill reduces stress in the solder joint. Because the mean impact life correlates to the maximum peeling stress by the Power Law, with the same reduction of stress, the improvement in impact life is greater in Zone 3 than in Zone 1 (ΔN3 > ΔN1).
Conclusion
The use of a properly designed underfill can significantly improve drop and bend tests, and the thermal cycle performance of BGAs. For both drop and bend tests, the components located where the boards bend are critical. Detailed consideration of a board’s mechanical design and product construction should be applied to minimize bending. For thermal cycling, results are not sensitive to the components’ positions on the board. To enhance thermal cycle performance, CTE mismatch between the solder joint, component, and board must be reduced.
References
Please contact the authors for a complete list of references.
* Zymet.
** Instron.
EDWARD IBE, senior development engineer, and KARL LOH, president, may be contacted at Zymet Inc., 7 Great Meadow Lane, East Hanover, NJ 07936; (973) 428-5245; e-mail: [email protected] and [email protected]. TONG YAN TEE, Ph.D., CAE team leader, and JING-EN LUAN, senior R&D engineer, may be contacted at STMicroelectronics, 629 Lorong 4/6 Tao Payoh, Singapore 319521; (65) 63507703; e-mail: [email protected].