Advanced packaging plays a critical role as semiconductor technology continues to fuel growth of new applications in consumer, healthcare, home, automotive, environmental and security markets. Packaging technologies help deliver the increased performance, low power, lower cost and smaller form factors that these applications require, and wafer chip-scale packaging (WCSP) has enjoyed significant growth over the past few years as a result of attributes to this end.
WCSP delivers reduced package footprints, lower costs, improved electrical performance and a simpler construction over conventional packages. An additional advantage is that the technology does not typically require underfill to meet board-level reliability requirements, and the implementation of enhanced co-design strategies should maintain this benefit into the near future.
As WCSP evolves, the integration of TSV interconnect technology will be required, enabling the stacking of ICs or other components to create highly integrated systems. TSV is an ideal solution for applications requiring higher performance, lower power and smaller form factors.
There are various configurations to stacked package assembly through TSV, and each has its advantages. The “via last” process (vias formed prior to wafer thinning within BEOL levels) is the most cost-effective solution as the TSV and back-side RDL are fabricated simultaneously. The “via middle” process (vias formed after completing WCSP wafer processing) is ideal for situations requiring fine-pitch and smaller via diameters, as those features address performance requirements and enable die size entitlement. Alternatively, final packaging could be standalone TSV-WCSP only, where components would be stacked similar to a package-on-package or embedded in a substrate or PCB laminate.
There are several development areas toward enabling stacked WCSP. These areas include TSV etch and plating steps, component stacking interconnect and assembly, and overmold material selection to minimize wafer- and package-level warpage. In addition, there are efforts underway to select wafer bonding adhesive and address the handling and shipping of thin (molded or unmolded) wafers or dies.
The transition to integrate TSV brings several reliability and manufacturabilty challenges. For instance, the addition of underfills and mold compound materials may change package moisture sensitivity levels. Managing warpage at the wafer level and final package level will become crucial to avoid SMT issues. In addition, TSV dies will be more prone to die cracking or dielectric and delamination issues. Collaborative efforts across the industry are underway today to address these issues.
WCSP is a mainstream packaging technology addressing customer requirements for lower costs and faster time to market, and demand for the technology continues to grow. As we move into the future, 3D structures will deliver increasing performance, smaller form factors and lower costs in semiconductor products.
— Dave Stepniak, Wafer-Level Packaging Manager, Texas Instruments