The semiconductor industry has become accustomed to the unrelenting march of progress led by Moore’s Law and the International Technology Roadmap for Semiconductors (ITRS), and takes somewhat for granted the miracle of two- or three-year rates of technology introductions. But in reality, technologies are rolled out over what takes typically at least 10 years. So if a manufacturer wants to be in the game, they need to be paying attention and going after prospective technologies very early.
Paolo Gargini, Intel Fellow and ITRS chairmanPaolo Gargini, Intel Fellow, director of technology strategy at Intel Corp., and chairman of the ITRS, detailed this point with example after example of similarly paced technology developments, and urged audience members to be thinking now for technology introductions beyond 2020. Gargini gave a keynote speech yesterday titled, “Welcome to the Next Decade!”
The CMOS process is undergoing a complete renovation that will further differentiate those companies that have developed an efficient means to bridge from risk research to high-volume manufacturing, according to Gargini. Much of what has transpired over the past couple decades has been predicted, including the end of classical scaling. But equivalent scaling techniques were long ago in the pipeline, so the transition from classical to equivalent kept progress on track.
For example, research initiated on strained silicon in the early 1990s went into manufacturing in the early 2000s, and research on high-k/metal gates in the mid-1990s went into manufacturing shortly after the mid-2000s. “I am confident that among the many possible solutions already demonstrated in research, we will continue to extract and introduce into manufacturing the next elements of equivalent scaling in a timely fashion,” Gargini said in a separate interview.
To that end, fundamental research has substantially increased. But it is no longer the domain of corporations, as it has shifted instead to universities, consortia, institutes and national labs. For any given research case, companies are able to select the most qualified universities on a particular subject, immediately access the expertise, and substantially reduce the time required to reach a fundamental understanding of subjects that may normally be outside the typical expertise of the corporation. At that point, consortia are useful to test the ideas in a pre-competitive environment. “Eventually, each partner company must do its own R&D work to adapt the best ideas to its product and manufacturing environment, and to differentiate its process technology for best competitive advantage,” Gargini added.
Intel, for one, has systematically applied a staged investment scenario to align the risks with the resources. It begins with external research at universities, for example; continues with research, evaluating a few options; pathfinding; development; and finally manufacturing.
According to Gargini, new device studies and process evaluations generated by the new approach have reached “unprecedented levels,” and have produced a new set of researchers from fundamental physicists to chemists and material scientists.
Some of the most innovative solutions that MOS technology has seen over the years include SiGe PMOS strained silicon, which made its debut in 2003. “This technology dramatically increased p-channel mobility, hence making it more efficient,” he said. In 2007, the introduction of high-k/metal gate (HKMG) reduced leakage by more than 100×, he added. “HKMG is the most fundamental change to the basic MOS transistor that the industry has seen in over four decades.”
Gargini gave special credit to George Scalise, president of the Semiconductor Industry Association (SIA) with keeping the semiconductor industry moving forward on the right roadmap because of his push behind the ITRS. And he credited the ITRS and its predecessor NTRS with predicting several significant developments that would enter manufacturing years later. The ITRS, for example, predicted in the 1990s that major innovations were going to be necessary to maintain device scaling at historical trends in the 21st century. A 1994 roadmap table also indicated EUV lithography as a key option for the evolution of lithography. “My opinion was that around 2010 would see something decent,” Gargini said.
Looking beyond 2020, Gargini said that Intel plans to keep all the CMOS logic benefits it has accumulated, but look at other new technologies such as spin transistors, quantum dots, carbon nanotubes, graphene and more. “Science doesn’t come with an instruction manual,” he said. “We’re doing all these experiments; who knows what we’re going to find out?”
— Aaron Hand, SEMICON West Daily News