Chemical mechanical polishing (CMP) has increasingly been recognized as an enabler for the fabrication of novel structures for MEMS and optoelectronics devices. Many of these applications require ultrasmooth surfaces and/or planarization of unique layers in order to function properly, and CMP is the only process capable of delivering the desired result.
Examples include planarization of thick oxides for MEMS, final step polishing of strained-layer germanium or SiGe structures, and surface roughness reduction for GaN, sapphire or other ultrahard materials. In many cases, determining the right combination of CMP consumables (pads and slurries) and tool process conditions is a major challenge, particularly when incoming surface conditions add to the variables that need to be understood before a successful process can be defined.
During the latest slowdown in the industry, the MEMS/optoelectronics market, as a whole, was outpacing the general market in revenue growth rate and R&D activities. New trends in MEMS and optoelectronics manufacturing are driving the need for CMP, but pose unique polishing challenges. MEMS require polishing of thicker oxide and polysilicon films and other non-CMOS materials. The polishing times for the thicker films and larger step heights can be significantly longer, meaning that process stability and consumable lifetime need to be monitored and addressed. Specialized slurry formulations are not always commercially available to create optimal polishing conditions to control removal rate, non-uniformity and defects, posing another challenge for process engineers.
Many of the new materials being integrated show non-linear polishing behaviors, while epi materials grown with lattice mismatch to the underlying layer are likely to require polishing to reduce surface roughness. For example, GaN epi can be grown on sapphire, transferred to another substrate, polished and the process is repeated. Low roughness, minimum defects and no contamination must be achieved or device parametric degradation can be realized. This is especially true for devices requiring direct wafer bonding (DWB). DWB require surfaces below 1 nm roughness, and CMP continues to be the best method to achieve this surface. Many TEOS surfaces encapsulating the new structures and materials can have an incoming surface roughness of >500 Å, but with an optimal process, a 3-10 Å final surface roughness can be achieved.
The success criteria for the CMP process for MEMS and optoelectronics manufacturing remains similar to that of semiconductors by understanding the following: film stack composition, layer thicknesses, incoming topography and post requirements, feature sizes and pattern densities, target thicknesses and uniformity requirements. Concerns that have resurfaced with the new materials and applications are film stress, mechanical integrity and delamination issues. By understanding the chemical interactions and process dynamics, solutions are able to be successfully implemented with the CMP process into novel devices, thereby enabling their functionality and accelerating their arrival into the marketplace.
— Jim Mello, Vice President of Sales/Marketing, Entrepix Inc.