The need for new memory structures, such as resistive RAMs (RRAMs), and through-silicon vias (TSVs) are presenting formidable materials challenges, speakers said at Wednesday’s TechXPOT on Advanced Processing and Materials.
There are “strong fundamental reasons” why RRAMs may emerge as a viable non-volatile memory, replacing floating gate flash at some point, said Paul Kirsch, director of front-end processes at Sematech. Memory researchers are investigating cross-bar arrays of RRAMs, which feature low power consumption at the bit level. With RRAMs also offering the prospect for low-cost processing, the memory could be embedded on SoCs or used in standalone memories. Kirsch noted that over the rest of this decade, high-end SoCs will be dominated by on-chip memory, with logic transistors accounting for 5% or less.
The RRAM research effort is focused on identifying the correct metal oxides, with nickel oxide as one of the promising materials to form the metal filaments that represent a memory bit. Etching and cross-contamination are major challenges. PVD is the likely process method to deposit RRAMs, Kirsch said, noting that “it is possible to stack planar layers on top of each other.” Moreover, if the uniformity of the RRAMs can be tightly controlled, it would be possible to create multi-bit-per-cell memories, much as NAND flash uses multiple levels of charge within each bit cell. A 4 bpc architecture is feasible, he said.
Dirk Wouters, an imec research manager, said conventional DRAMs are reaching scaling limits on several fronts. The aspect ratio of the capacitors is headed toward 50:1. Also, the high-k dielectrics used in the DRAM cell must be improved. Hafnium oxide may be replaced by zirconium oxide, with a k value of 40, and later with strontium titanate (SrTiO) and BaSrTiO. “Nature is not helping us, because the high-k materials have a lower bandgap, resulting in higher leakage,” Wouters said.
The track record of floating-gate NAND flash scaling has been impressive, with density doubling every year. But Wouters said at the 20 nm node, only 100 electrons will represent a bit, leading memory companies to develop alternatives such as charge-trap memories, and memories that stack vertical transistors within the die. With these vertically stacked transistors, manufacturers could relax the lithographic dimensions to 50 nm, for example.
“RRAMs represent a major materials challenge,” Wouters said, adding, “Nickel oxide etching is a serious issue at this moment.” At imec, MOCVD tools have created 8 nm thick layers of the metal oxides, but atomic layer deposition can achieve 5 nm.
On the logic side, Wouters said the industry will shift to multi-gate transistors, supported by 3D solutions with TSVs. Channels based on germanium and III-V compounds are likely. Further out, companies may be able to incorporate carbon nanotubes, nanowires and graphene.
Two speakers looked at TSV-related challenges. Sesh Ramaswami, a strategy manager at the TSV program at Applied Materials, described the equipment and materials challenges represented by TSV-enabled chips, which he said are “in various stages of late development.”
The vias-middle approach creates the TSVs after the contacts, in a fab-based process. Later, the wafers are thinned and backside contacts are created. In the vias-last flow, TSVs are formed from the backside after the wafer is thinned. While many of the TSV process steps are extensions of etch, deposition, plating, CMP and metrology steps, TSV chips will require new learning. Temperatures must be held to relatively low values, and bonding, handling and transporting the thinned wafers represent hurdles the industry will need to overcome. “The adhesive bonding and debonding is new to the industry,” Ramaswami said, adding that “much work remains to be done on standards.”
Robert Geer, an interconnect researcher and professor at the College of Nanoscale Science and Engineering in Albany, N.Y., presented research on ways to use TSVs to meet the bandwidth needs of tomorrow’s ICs. For ICs that process video, or on-chip RF modules, the bandwidth demands are enormous. For memory access, bandwidth of 2 Tbps is sufficient, but logic-to-logic computation requires 5-6 Tbps, and RF signals need even higher rates.
“As nice as TSVs are, they are still copper, which has a frequency limit of about 1 GHz,” Geer said. By surrounding a signal TSV with four other TSVs used as shields, designers could accomplish the on-chip equivalent of a coaxial cable, achieving much higher bandwidths. Designers must balance their need for higher bandwidth with the fact that TSVs require space. “Every time we are using a TSV, we are losing device area,” Geer said.
— David Lammers, SEMICON West Daily News