TSV Interposers and True 3D ICs using TSV
Through-silicon vias (TSV) have been in R&D for more than 10 years and are finally scheduled to reach commercial use in IC manufacturing this year. Vias will be made through silicon both in active ICs (3D-IC) and though silicon interposers (2.5D) made in outsourced test assembly and packaging (OTAP) fabs.
Many workshops and TechXPOTS at SEMICON West this year will deal with the real-world issues of commercial manufacturing of TSV, including supply-chain business models and the need for new EDA models. On Wednesday morning, July 13, from 9:00am to 12:00pm in the San Francisco Marriott Marquis hotel, SEMI/SEMATECH will hold a workshop on “3D Interconnect Challenges and Need for Standards.”
Different original equipment manufacturers (OEM), specialty materials suppliers (SMS), and consortia have created TSV along parallel private roadmaps. In addition, there are “boutique” companies providing custom 3D-IC advanced-packaging services for military and aerospace applications looking to expand into high-volume commercial markets. The result is a confusion of options, and no real cost or yield data for volume manufacturing. Nonetheless, after more than 10 years of R&D and pilot work, TSV are finally scheduled to be produced this year in limited commercial volume.
After considering the many options to form TSV through active silicon, the world has settled on two:
- Via-Middle, TSV after transistors and tungsten but before multi-level Cu interconnect, with 3 to 5 micron diameter and 50 micron deep vias etched “blind” into full thickness wafers in the fab, and
- Via-Last, TSV etched to a stop layer from the backside of thinned wafers temporarily bonded to carriers at an OTAP, with 8 to 10 micron diameter and 50 to 100 micron deep vias.
The via-middle TSV etch being “blind” means that it never sees a stop layer and just etches for a certain time, creating a greater challenge for controlling uniformity in etch chambers.
For interposers made using silicon wafers, the final target thickness will be 100 to 140 microns. Interposer thickness cannot be reduced below 100 microns without rigid silicon wafers becoming flexible silicon foils that generally cannot be handled by automated robotics. Typical TSV processes to date have worked with 5 to 10 micron diameter vias, which results in the need for integrated process flows capable of etching and filling 10:1 to 20:1 aspect ratio (AR) structures. Silicon interposers (2.5D) have near-term applications including high performance network systems, laptops, tablets, mobile systems, and game consoles.
Georgia’s Institute of Technology (GT) has a Packaging Research Center (PRC) that has been working on TSV and 3D packaging under packaging guru Rao Tummala. At a SEMI-sponsored pre-show webinar, Prof. Tummala discussed some of the ways to reduce interposer costs using panels of poly-silicon instead of wafers of single-crystalline silicon. Starting with 200-micron thick poly-Si sheets, Tummala’s process uses lasers to drill vias and then a polymer deposition to form insulation instead of oxidation. Glass could be used as the interposer material with advantages for some applications (figure), so there are now many different applications for silicon or glass interposers (SiGI).
Will silicon interposers be a temporary stop or a solid fork in the highway for 3D progression? How will silicon interposers integrate with Cu pillars? How should the industry tackle memory stack assembly with TSV? Speakers including Prof. Tummala will discuss possible answers to these and related questions on Wednesday afternoon, 1:30pm to 5:00pm, in the Moscone NorthOne TechXPOT, when the SEMI Advanced Packaging Committee of the Americas will host “3D in the Deep Submicron Era.”
– Ed Korczynski