This is Part 2 of the story; Part 1 can be found here.
by Debra Vogler, Instant Insight, Inc.
Lithography: building an infrastructure
Stefan Wurm, SEMATECHSEMATECH has been contributing to building an EUVL infrastructure via its Mask Blank Development Center (MBDC) and its Resist and Materials Development Center (RMDC). The consortium’s two microfield exposure systems (METs) have been enabling the resist and materials infrastructure to introduce EUV at the 22nm hp while exploring extendibility to 16nm. “The METs have operated at higher uptime, and utilization of RMDC tools has increased, as has the total of imaged wafers across all tools,” noted Wurm. The consortium has evaluated more than 2000 new EUV materials formulations that target the sub-22nm hp nodes. According to SEMATECH, the RMDC’s capabilities allow resist and material suppliers to gain access to the highest-resolution optical imaging available as well as to the high throughput that resist and materials samples require for early stage development. Wurm also reports that the MBDC has demonstrated new champion data of a total of 6 particles on an EUV mask blank at >50nm sensitivity, which surpasses the best recorded results of 26 particles at >50nm sensitivity.
While work on resists and masks throughout the industry has been ongoing, experts say that more work needs to be done to study the physical properties of mask materials. According to Franklin Kalk, EVP & CTO at Toppan Photomasks, such properties as refractive indices and elemental composition need to be evaluated. Similarly, Kalk is interested in mask durability under HVM conditions, which is not possible until there is a source with the requisite power available.
A breakthrough in resist development was reported at this year’s SPIE Advanced Lithography Conference (2/12-2/16/12, San Jose, CA), whereby 16nm hp at 33mJ/cm² was achieved. However, to meet EUVL throughput targets, the sensitivity has to go below 20mJ/cm². Some experts question whether the usual trade-off among resolution, line-edge roughness, and sensitivity can be met. For example, Kalk isn’t sure resists in the 10-15mJ/cm² range are doable for EUV. “There won’t be enough photons to give good line-edge roughness (LER) at that kind of dose,” said Kalk. “I think we’ll probably be looking more at about 25mJ/cm² resists.”
New materials and processes for sub-22nm devices
Intel has continued its pursuit of improved transistor performance – particularly at low voltages – with its tri-gate architecture. And though such performance at low voltage and low power are needed for consumer electronics, Kaizad Mistry, VP, director of logic technology integration at Intel, told SEMI that it’s also required for high-performance servers. The company plans on using the tri-gate structure, which was announced in 2011, not only for the 22nm node, which is already in production, but also at 14nm. According to Mistry, the company expects to be in HVM for 14nm by 2H13.
Mistry noted that there are advantages to being an IDM when bringing new technologies to market. “Whether it’s design tools that need to change…or mask making that needs to change, or fab process tools that need to change – we can adapt and get those things done more easily as an IDM,” said Mistry. He added that collaborating internally is easier than collaborating across corporate boundaries, thereby facilitating bringing new devices to market sooner.
Continuing transistor scaling beyond 22nm will require not only the eventual adoption by all of a type of 3D device (e.g., FinFETs, tri-gates), but the use of high-mobility channel materials (Ge or III-V materials) on silicon to meet power dissipation requirements. According to Raj Jammy, VP, emerging materials and technologies at SEMATECH, the point at which a given company will adopt a 3D transistor architecture along with high-mobility channels depends on its specific products and applications. Jammy, however, believes the point at which everyone will have to switch to 3D+high-mobility will most likely occur at 11nm and below.
The move to Ge and III-V materials will be challenging and Jammy says that in order for the materials to be ready in time, the industry has to start thinking about tackling the challenges now. Among the challenges are the deposition of high-quality III-V layers on top of silicon – and doing so cost-effectively with low defect density. Additionally, the making of junctions will be different when using III-Vs because implantation cannot be used. Other challenges include selecting the contact material: gold is used now with III-V materials that are on III-V substrates; but gold cannot be used with III-Vs on silicon because it diffuses rapidly into silicon and changes the device characteristics. Despite the daunting list of challenges, experts maintain that the benefit of using high-mobility materials is the ability to enable greater functionality (for example, SoC) on chips.
One technique being evaluated by imec researchers – aspect ratio trapping (ART) – is expected to offer a lot of flexibility for heterogeneous integration. According to Aaron Thean, director, logic program, at imec, ART is a way of growing highly mismatched materials in tight trenches. The defects that form can be terminated on these highly confined structures, he said. So as the crystal grows up the trench, the material will relax, forming defects that tend to terminate on the sidewalls of the trenches. At some point, most of the defects will end up on the sidewalls leaving a less defective material at the top of the growth, explained Thean. This less defective material can then be used as the channel material for the device. The flexibility arises from the ability to use ART to grow different materials in different trenches on the same wafer/chip. So for example, Thean noted that one could grow III-V in some trenches, and in other trenches one could grow Ge – all on the same wafer/chip.
The College of Nanoscale Science and Engineering (CNSE) at the University at Albany is also working on sub-20nm technologies. The research organization is collaborating with equipment suppliers to evaluate new techniques for ultra-shallow junctions. Christopher Borst, assistant VP for module engineering at CNSE, told SEMI that Nissin Ion Equipment is working with CNSE to engineer the incorporation of a Si:C layer into the source/drain region of NMOS transistors to improve drive current. “The joint work evaluates Si:C stressor layer formation by molecular carbon (cluster carbon) implantation with a suitable combination of anneal conditions,” reported Borst. “The collaboration is intended to study the combined effect of C cluster implant followed by a rapid thermal anneal and subsequent laser anneal for dopant activation (Fig. 2).” According to Borst, among the requirements for this combined process is that it must result in a beneficial strain property and defect-free recrystallization of the Si:C layer.
A 60nm thick amorphous layer formed by the cluster implant, and the HRXRD data showing an ~1.5% carbon substitution after spike RTP anneal. Source: CNSE
CNSE is also conducting TCAD simulation of nonplanar device geometries scaled to 20nm FinFET widths and below. To address scaling down to 1Xnm and below, CNSE is also developing alternative channel FinFET integration schemes by using an infrastructure of advanced process tooling available at the college (e.g., litho, dry etch, wet etch, and thin film). “We are creating extremely aggressive test structures both in bulk material architectures and in replacement gate strategies,” reports Borst. “This will allow us to explore Ge and eventually III-V FinFET devices at sub-10nm dimensions.”
Practical considerations
As the industry works to develop the materials and processes for advanced ICs, there are some practical considerations – namely, the design of process equipment – that also have to be addressed. And cost is, again, a primary driver. As features become ever smaller, the impact of impurities and defects on yield become even more significant below 22nm. Taking additional steps to prevent flaking, particulates, and delamination off process chamber walls is critical at 20nm and below, but one of the most desirable materials for this task that has a low erosion rate (yttrium, according to Advenira SVP, business development, Andrew Skumanich) is also the most expensive. Other choices such as a standard aluminum oxide or aluminum nitride, are relatively inexpensive, but not effective enough below 20nm.
Andy Skumarich, AdveniraAdvenira has developed a liquid deposition process in which the liquid is converted to a solid that is comprised of glass-like elements: a mix of silicas, carbides, and nitrides. The exact composition depends on the part/application (shower heads vs. chamber rings) and what kind of protection is required. The coating is conformal, said Skumanich, and it can be tuned such that thermal expansion coefficient matching can be accomplished. This feature is important to prevent problems with process chamber components that see frequent thermal cycling (i.e., mismatched coatings delaminate, creating particulates). Skumanich also noted that the company’s process provides a two orders of magnitude improvement in erosion resistance to the most aggressive fluorine chemistry compared to standard composites, yet is lower cost than Yt-based approaches.
Debra Vogler is president of Instant Insight Inc., 370 Altair Way, PMB #234, Sunnyvale, CA 94086; email [email protected]