Mark Bohr, Intelby Jeff Dorsch
Intel has resorted to “non-classical” scaling in making its 22-nanometer generation of chips, including the new third-generation Core “Ivy Bridge” processors, according to Mark Bohr, a senior fellow at the chipmaker and the company’s director of process and integration.
Giving the keynote address at Monday’s SEMI Gartner Market Symposium, titled “Silicon Technology Leadership for the Mobility Era,” Bohr summarized how Intel has done scaling of IC dimensions over the past two decades. “The ‘golden era’ of traditional or classical scaling served well for a long time,” he said. “But we were paying a price – leakage current,” Bohr added.
Classical scaling came to an end more than a decade ago with Intel turning to strained silicon technology for its 90-nanometer generation of devices in 2003, he noted. At the 45-nanometer node, and continuing with the 32-nanometer generation, the company resorted to another “non-classical” scaling technology, with high-K metal gates.
With the 22-nanometer generation, Intel has moved beyond planar transistors to tri-gate/finFET three-dimensional transistors, Bohr said.
“Intel is no longer a ‘one size fits all’ company,” he noted. “Now we are supporting a wider range of products. We know how to make a high-performance, low-power chip.”
That chip in particular is the “Medfield” Atom processor, which has 423 million transistors. The chip is made with Intel’s 32-nanometer P1269 system-on-a-chip process, according to Bohr. In the 32-nanometer generation, Intel developed both CPU and SoC versions of the process, and that differentiation has continued into the 22-nanometer generation, with the P1270 (CPU) and P1271 (SoC) versions.
The “Ivy Bridge” processor and other 22-nanometer chips are “a fully depleted device,” where the gate electrode has “more complete control,” he said. These chips have a lower voltage than devices based on planar transistors, with a 50 percent reduction in active power, Bohr added.
Oh, and “Ivy Bridge” has 1.4 billion transistors.
Intel currently has three wafer fabrication plants producing 22-nanometer chips, with another two coming on line by the end of the year, according to Bohr.
While 22-nanometer chips are in volume production today, Intel is currently developing 14-nanometer devices, and its research group in Oregon is “exploring a wide range of devices,” Bohr said. “Not everything they work on will pan out.”
He noted that Intel first published a paper on tri-gate technology in 2002, and it took another nine years before the technology was being used in volume manufacturing.