by Debra Vogler, Instant Insight Inc., Sunnyvale, CA
Though industry experts can debate which is the better transistor architecture solution (non-planar or ultra-thin SOI) to control short-channel effects and leakage on the path to sub-14nm technology, there is no debate that new channel materials will be needed. Paul Kirsch, director of front end processes at SEMATECH, expects germanium (Ge) to enter the roadmap first as an enhancement for pMOS FETs in a non-planar architecture. Because III-V materials are more challenging to integrate, Kirsch expects those will come into play most likely beyond the 10nm node. “Depending on the success of our development efforts, you could see the presence of some Ge at 14nm as a channel material, but it’s unclear at this time if it would take the form of SiGe or a pure Ge material,” said Kirsch. “Both are possibilities at 14nm.”
A major challenge is developing a low-cost process technology to deposit III-Vs and Ge on top of silicon. “Ge process technology has progressed nicely because SiGe is already used for a source/drain stressor material,” observed Kirsch. “So the issue isn’t so much with Ge but with III-V molecular beam epitaxy (MBE).” MBE requires expensive tools and specialized operators and uses a lot of expensive consumables, Kirsch noted. And, he added, the throughput is not high. Because of these drawbacks, he believes that metal organic chemical vapor deposition (MOCVD) might be required for III-V high-volume manufacturing (HVM) on a silicon substrate.
As with just about every new process or material integration effort, implementing MOCVD is not going to be easy. Kirsch cites the lack of 300mm tools suitable for HVM MOCVD (only beta versions are in development), the difficulties in handling the materials, and the environment, safety, and health (ESH) issues. Defectivity is also problematic. “Silicon and SOI substrates have very low defect densities – probably below 1000 or even below 100 defects/cm²,” said Kirsch. “But III-V is typically closer to 1×108 defects/cm², so growing a film with a lower defect density and engineering the process equipment to enable that lower defect density are key challenges.
The monitoring and control of new processes developed for new materials will also pose challenges for metrology suppliers. Lanny Mihardja, product marketing manager, FaST division at KLA-Tencor, reported that the company’s customers are in the process of characterizing blank film stacks for III-Vs and Ge with respect to optical properties. “As time goes on, they will start looking at how they want to shape and design the composition of these materials [III-Vs and Ge] into their structures, and eventually, deciding how these new gates will be formed.” Even if 3D structures and shapes are not yet available, evaluating the blank film stacks is difficult enough because a multiple film stack has to be measured to be able to deduce the optical properties, thicknesses, and indices of refraction – all prerequisites to being able to tackle the shape and CD measurements.
Aside from the technical challenges associated with the growing importance of new materials at 14nm and below to support deposition processes, including patterning technologies, there is the market potential to consider. Mark Thirsk, managing partner at Linx Consulting, believes that the market for advanced materials will grow faster than the semiconductor device market (Fig. 1). “In 2012, advanced materials are just under 2% of the total cost of semiconductor revenue,” said Thirsk. “By 2020, we think that will be closer to 3.5-4%.”
Figure 1. Process materials requirement as a percentage of semiconductor revenue. SOURCES: Linx Consulting, IC Knowledge