by Debra Vogler, Instant Insight Inc.
Making good on its 22nm Tri-gate announcement last year, Intel is already ramping to high volume with its 3D (fully-depleted) transistor architecture. Among the benefits are a reported 37% performance increase at low voltage and >50% power reduction at constant performance. In a pre-SEMICON West interview, Kaizad Mistry, VP, director of logic technology integration at Intel said the company plans to extend its Tri-gate technology to 14nm. Thus, the race to get below 22nm is already in progress.
There is another camp, however, that suggests it would be better for IC manufacturers to not make the leap to both a 3D structure and fully-depleted transistors in one step, as Intel has done. “At 28nm, the industry is already struggling with managing leakage and driving yields,” observed Steve Longoria, SVP, business development at Soitec. “So this is a red flag on the field of our industry and it will be even worse at 20nm. Many companies are questioning if they should even do a bulk CMOS solution at 20nm.”
By using silicon-on-insulator (SOI)-based technology as a “bridge,” the industry can get the performance benefits of a fully-depleted transistor while staying with a planar transistor at 28nm and down to 14nm (or sub-14nm), when some sort of FinFET or tri-gate type of structure will likely be required. “With a fully-depleted planar architecture, you can take advantage of the power performance jump,” said Longoria. He noted that STMicroelectronics’ decision to go with SOI-based technology [the FD-2D wafer] at 28nm enables a 40% power performance bump over bulk silicon. “The fully-depleted two-dimensional solution enables a more regular migration for the industry,” meaning that it’s not a huge leap for the foundries and the design ecosystem/EDA/IP sectors. “One can stay with the same manufacturing process, same manufacturing tooling, same design flow, and same IP.”
Soitec’s solution for when the industry must move to a FinFET or tri-gate type structure is the FD-3D SOI wafer, which pre-integrates critical characteristics of the transistor within the wafer structure. For its FD-3D wafers, explained Longoria, “We’ve preset the height of the fin at the wafer layer and taken out significant front-end process steps that more than outweigh the cost adder of the wafer.” (Fig. 1). “Because we have this buried oxide under the fin, where we’ve fixed the height, you no longer have to do all your isolation processes between fins (such as STI and high-energy implant under the fin).”
Figure 1. A Fin-first process on FD-3D. SOURCE: Soitec
Longoria added that if the industry can reduce a few mask sets and do pre-processing, it’s a huge cost savings. “It’s moving some of the complexity out of the foundry and into the wafer manufacturer to result in a lower cost system-on-chip (SoC),” said Longoria. He also observed that if a company were to start today and try to implement a FinFET process, the estimate from companies such as IBM is that it would take 5 to 7 quarters less development time using the SOI wafer because of the steps that don’t have to be developed. Longoria pointed out that IBM is committed to using SOI for its FinFET offering starting at 14nm, including server processors and ASICs. Among the benefits of FD-3D technology that he says are important to IBM are the reduced process complexity, which offsets the wafer cost, and a better soft-error rate immunity. Between its two SOI-based solutions, Longoria says there is an early, low-risk migration at the 28nm down to 10nm and beyond.
Looking ahead, Soitec will be adding strained silicon to both its FD-2D and FD-3D product lines, with preproduction expected no later than 2014. Beyond the 14nm node, the company is also researching the use of Ge or III-V materials, as well as new transistor architectures, such as nanowires. Longoria said the company’s technology is fully scalable to 450mm wafers, and it will be ready well ahead of the industry’s need, though as of this writing, 450mm sample wafers have not yet been made available.
Equipment suppliers getting ready for sub-2Xnm
Two critical processes needed for making transistors are implantation and annealing. Applied Materials launched its latest Applied Varian VIISta Trident high-current implantation solution a few weeks before SEMICON West. Targeting sub-2Xnm transistors, the company believes that the horizontal and vertical angle control feature on the new implanter will be important for 3D transistor manufacturing, though Tom Parrill, high-current marketing director at Applied, said the company could not discuss applications of the tool for 3D transistors at this time. Going forward, Parrill said that the new system – based on proven ribbon beam design technology – is believed to scale very well to 450mm wafers.
Ultratech’s laser spike-annealing (LSA) technology is being developed for 20nm as well as sub-20nm nodes. “For the foundry market, it’s still planar transistors,” explained Jeff Hebb, VP of laser product at the company. “No one is going to FinFET or 3D structures [the foundries] at 20nm as far as we know.” Therefore, traditional users of advanced annealing, such as LSA, still need to activate dopants at 20nm, he explained. And though Hebb doesn’t expect to see more junction activation steps in going from 28nm to 20nm, he says there is a trend to do more non-junction activation steps where either millisecond annealing or LSA is being used.
Ultratech is already working with its customers to use LSA to improve the device performance of FinFETs (Fig. 2). “We see no showstoppers to apply LSA to FinFETs,” noted Hebb. “In fact, our advantages (minimal pattern loading effects and no hot spots) might even get a little bit wider.” Furthermore, the company does not think implant will go away; instead, it is believed the industry will end up using a combination of epi plus implant. “Even if you deposit an epi film, our customers are telling us that, to get maximum activation, LSA is beneficial.”
Figure 2. Planar transistor at 20nm showing LSA applications for front end and middle-of-line: a) traditional junction activation applications for which LSA has been used in previous nodes, and b) new applications that are expected to utilize LSA for the 20nm node. Applications are expected to be similar in regards to LSA for 3D structures at 14nm. SOURCE: Ultratech
Last thoughts
Paul Kirsch, director of front end processes at SEMATECH, told SEMI that he believes that each company will decide for itself what makes sense for its product set – either nonplanar architecture or ultra-thin SOI – to control short channel effects and leakage. “Intel is using tri-gate, but there are a lot of other papers published at conferences and journals that show other approaches,” said Kirsch. In the long run, however, he noted that the industry usually coalesces around one approach because that makes sense from infrastructure and cost standpoints.
Acknowledgements
VIISta is a registered trademark of Applied Materials.