Fab Challenges for 22nm Include FinFETs and Emerging Architectures
The imminent switch to a vertical transistor by the world’s largest semiconductor company – after 50 years of planar ICs – has experts gauging the impact of Intel’s fully depleted tri-gate announcement on the wider semiconductor industry.
Will foundries such as TSMC accelerate their plans for a finFET-based technology platform at the 16/14nm node? (As one equipment executive put it: “The big fabless companies already are asking their foundry partners: ‘When do I get my finFET?’”)
Will some companies prefer an ultra-thin-body planar SOI platform, believing that yields will be higher, costs lower, and power consumption as good as that of finFETs? Will companies such as IBM, which has an embedded SOI DRAM, use SOI wafers for a finFET architecture? And will startup SuVolta, with its claims to a low-power technology in a bulk (non-SOI) planar CMOS, garner adherents?
These questions will arise this morning (July 12) at the Emerging Architectures for Logic and Memory TechXPOT, planned for 10:30am to 12:30pm in the North Hall of the Moscone Center. To be sure, by the 16/14nm node the industry will shift to a fully depleted architecture for improved short channel control and less sub-threshold leakage, said Serge Biesemans, vice president of process technology at IMEC and one of the speakers at today’s TechXPOT.
FinFETs with a fully depleted channel, Biesemans said, turn on faster, allowing companies to target a lower threshold voltage, delivering higher drive current and faster circuit speeds. Intel claims that its 22nm tri-gate will be 37 percent faster than its 32nm planar transistor at 0.7 Vdd. That may allow Intel to run its 22nm MPUs at a Vdd of about 100 to 200 mV less than its 32nm processors, providing a 50 percent power savings at the device level.
Manufacturing Challenges
The advantages of finFETs depend on solving several manufacturing challenges, ranging from lithography to implants to etching and beyond. Indeed, University of California at Berkeley professor, Chenming Hu, argues that in the early going only the deep-pocketed companies such as Intel, TSMC, and one or two others may be able to deliver finFETs at acceptable yields.
With finFETs, the height of the fin is equivalent to the channel length, and the fin width must be kept to half of the fin height. Controlling these two dimensions precisely is one process challenge.
Kaizad Mistry, the 22nm program manager at Intel’s Technology and Manufacturing Group in Hillsboro, Ore., said a skinnier fin is needed to provide the fully depleted behavior, as well as to control short channel effects. However, “if the fin is too skinny, then current resistance gets larger. Too wide, and we don’t get nice fully depleted behavior,” he said.
There is a similar tradeoff for the fin height. A taller fin delivers more drive current, but at a higher gate capacitance. “It depends on the type of circuit, whether it has more interconnect load or more transistor load,” Mistry said.
Because the narrow fins are undoped, said Biesemans, work function engineering (WFE) depends primarily on dual-WF high-k/metal gate steps. And the narrow fins are difficult to recrystallize, requiring adjustments to the annealing steps. Source and drain regions present new challenges: selective epitaxial growth on the undoped fins require careful implants in the source and drain regions, he said. Strain engineering on the vertical transistors requires other changes.
Solutions Matter
How companies solve these issues will dominate the technology agenda for years. FinFETs based on silicon channels may share the stage with UTB-SOI at the 16/14nm and 12/10nm nodes. Beyond that, researchers may try to bring in higher-mobility channel materials, perhaps introducing silicon germanium in the pFET and III-V materials in the nFET, on either vertical or planar structures. Raj Jammy, Sematech’s VP of materials and emerging technologies, will discuss these heterogeneous technologies at the Emerging Architectures TechXPOT. The third speaker will be Ali Khakifirooz, the ETSOI lead device engineer at IBM Research.
And what may be doable for Intel, with its ability to dedicate fabs to just a few mask sets, may be a much tougher manufacturing challenge for foundries. “The biggest challenge with the tri-gate technology is to have a robust manufacturing process, to pattern the fins with the required fidelity of the fin width and height, and do it for billions of transistors,” said Mistry.
Hu, who led a Berkeley team that proposed a workable finFET a dozen years ago, said “initially, these transitions are going to be so very difficult, but if the right amount of time, money, and people are invested, they can get it done.”