3D Structures and Stacking Lead to New DFM
There are incredible changes sweeping the industry as leading-edge commercial fabs begin to ramp 22nm node chips. Partially-depleted planar transistors in bulk silicon have been used for the last 50 years, but must finally be replaced with fully-depleted (FD) channels. Both 3D multi-gate/“finFET”architectures and SOI (FD-SOI) wafers can full-deplete channels, however, so these technologies seem mandatory for logic and mixed-signal SOCs in the near future. Stacking chips in 3D using through-silicon vias (TSV) is being done in multiple pilot lines. Managing all of this new 3D requires new tools and methodologies in design for manufacturing (DFM).
The hundreds of interdependent process steps that must be controlled in a modern CMOS IC fab evolved in harmony over the last 50 years. Resolution limits of the old process flows, however, now require us to think in completely new dimensions. Patterning below the resolution limit of lithography requires the use of 3D stacks of sacrificial patterning layers along with the resolution burden being transferred to etch. Memory cells constrained by area move into the next dimension for storage nodes and transistor layouts.
With design and mask costs increasing, and with greater emphasis on consumer electronics demand surges that drive high-volume manufacturing (HVM) at advanced nodes, the cost of design failure becomes ever greater. DFM today can include design for test (DFT) and design for e-beam (DFEB) maskmaking to ensure that the first silicon reaches market.
3D Structures
Intel has announced that the “tri-gate” finFET will be the company’s 22nm transistor technology for high-volume manufacturing (HVM) of digital ICs. With much of the IC fab world focusing on low-power chips for mobile applications, the fully-depleted channels of finFETs provide reduced power consumption. However, there are 2nd-order electrostatic issues associated with the 3D structures so that new possible leakage paths must be controlled. Intel’s use of finFETs is also noteworthy because both compressive and tensile strain have been retained from planar devices. Meanwhile, leading commercial foundries TSMC and GlobalFoundries have both officially declared that they will not need finFETs until 16/14nm.
At IEDM 2010 (S05P03), researchers from North Carolina State University (NCSU) working for Intel and the National Science Foundation (NSF) demonstrated that properly engineering sandwiches of Hf-based high-k dielectrics — in combination with TaN metal floating- and control-gates — reduce gate-to-gate leakage, allowing NAND Flash scaling down to 1Xnm nodes. DRAM can be extended to 22nm node and smaller by using ALD and extensions of other deposition technologies that provide conformality in forming MIM stacks inside of extremely high aspect-ratio (AR) structures.
3D Stacking
Through-silicon vias through ICs (TSV-IC) have been in R&D for over 10 years and are finally scheduled to reach commercial use in IC manufacturing this year. Vias will be made through silicon in DDR3 DRAM dice to reduce size and power consumption for mobile devices, as scheduled for sampling by Elpida in the 2H11. Typical TSV-IC processes have used 5:1 to 10:1 ARs for chips 10 to 50µm thick.
TSV through interposers (TSV-interposer) will be made by many outsourced test assembly and packaging (OTAP) fabs. For interposers, the final silicon target thickness will be 100 to 140µm. Interposer thickness cannot be reduced below 100µm without rigid silicon wafers becoming flexible silicon foils.
Georgia Institute of Technology (GT) has a Packaging Research Center (PRC) working on TSV and 3D systems under packaging guru Rao Tummala. Professor Tummala has shown how to create the most cost-effective silicon interposers using panels of polysilicon instead of wafers of single-crystalline silicon. Starting with 200µm thick sheets, Tummala’s process uses lasers to drill vias and then a polymer deposition to form insulation.
On the afternoon of Tuesday, July 12, at SEMICON West, a paid workshop will be held at the Marriott Marquis hotel on SEMI Standards for TSV commercialization. Also on Tuesday afternoon, at the Moscone Center NorthOne TechXPOT, the SEMI Advanced Packaging Committee of the Americas hosts a free conference on “Heterogeneous integration with MEMS and sensors.”
On Wednesday morning, July 13, from 9:00 am to noon in the San Francisco Marriott Marquis hotel, SEMI/SEMATECH will hold a workshop on “3D interconnect challenges and need for standards.” On Wednesday afternoon, from 1:30pm to 5:00pm in the Moscone NorthOne TechXPOT, the SEMI Advanced Packaging Committee of the Americas will host “3D in the deep submicron era,” which includes Prof. Tummala as a panelist.
DFM
With the source wavelength for lithography stuck in water at 193nm, and all post-optical “next-generation lithography” (NGL) technologies still stuck in R&D, the only way today to form 32nm and smaller structures is to use clever extensions to optical litho like double-patterning (DP) and source-mask-optimization (SMO). Such extensions require integration of design and manufacturing technologies to an ever greater extent. DFM is only possible with accurate fab data, so to design ever-smaller devices, the industry needs ever more capable measuring tools.
Electron-beam (e-beam) lithography has long printed the photomasks used for chip production, but the best vector-scanned e-beam writers can still take ~80 hours to write a single mask at the 22nm node. Design for e-beam (DFEB) along with cell projection e-beam exposure tools can reduce the time needed to write a 22nm-node mask to <30 hours, according to the e-Beam Initiative.
On Wednesday morning, from 10:30am to 12:45pm in the Moscone NorthTwo TechXPOT, SEMI will host back-to-back “Design and Manufacturing” panels: yield improvement methodologies, and the influence of 2.5/3D chip stacks on the global supply chain.