Future 3D Chips May Need 1D Litho
Lithography alone always used to define the smallest lines on ICs, but affordable patterning for 22nm node and beyond will require contributions from engineers working in not only lithography but also design, etch and deposition. The Advanced Lithography session Wednesday morning from 10:30am to 12:30pm in the NorthOne TechXPOT in Moscone Center will feature the latest updates to the EUV lithography infrastructure, ways to push optical lithography past the normal resolution limits, and ways to complement optical lithography with E-beam direct write (EbDW) technologies for future nodes.
The EUV lithography infrastructure of steppers, 13.5nm wavelength sources, and resists continues to improve, but it seems to have missed the insertion time for 22/20nn node manufacturing. Thus, 193nm wavelength immersed in water (193i) steppers will have to be used for the next node again. The Metal-1 pitch for the 22/20nm node will be ~64nm, which is well below the 80nm limit for single exposure. Double-patterning (DP) using various approaches will have to be used, which creates new challenges for EDA, and mask-makers will have to manage layer fractioning.
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At IEDM 2010, Samsung researchers showed sidewall spacer double-patterning (SSDP) will be used for 2Xnm half-pitch Flash chips, but in a variation Samsung terms “self-aligned reverse patterning” (SARP), where the sidewalls define the pattern instead of the cores/spaces. The CD uniformity of SARP is reportedly <5%, compared to >10% when trying to use the cores/spaces of self-aligned double-patterning (SADP), and the improved uniformity reduces threshold voltage (Vth) distribution.
After Double Patterning a Single Dimension
The only way to regain manufacturing margin in lithography is to sacrifice a degree of freedom in design and restrict all patterns in a mask to arrays of parallel line segments, just as Intel has been doing for the last few nodes. In so doing, dipolar and other off-axis illumination can be combined with phase-shifting masks to squeeze the 193nm light into the smallest possible grating patterns.
Pushing the limits of 1D design is possible with double-patterning (DP) when gridded design rules (GDR) are used to make uniform arrays, followed by pitch-splitting, a.k.a. frequency multiplying, to get to sub-wavelength resolution features and a final “cut” pattern of selectively placed orthogonal line segments (figure). The cut layer thus becomes the most critical in terms of lithographic parameters, with similarities to the hole patterns used in contact layers.
At the SPIE Advanced Lithography conference held earlier this year in San Jose, Valery Axelrad of Sequoia Design Systems and Michael Smayling of Tela Innovations presented results from collaborations with Canon on “Optical lithography applied to 20nm CMOS logic and SRAM.”
Optimization variables for the cut layer include the cut geometry (width, height, serifs), illumination of the scanner lens entrance pupil, and grouping cuts in similar optical environments to allow for local OPC. The optimization was for the CD error across all cuts, which also reduces variation among cuts by getting all CDs close to the same target value. This reduction of variation substantially simplifies the layout and OPC and produces manufacturable designs, including both SRAM and logic.
There are many ways to formalize GDR+cut DP litho, but Tela and partners propose the following 1D rules:
- Highly uniform 1D GDR layouts with sparse identical cuts,
- Critical layers are cuts,
- All cuts identical to each other and tripled to ensure yield,
- Cuts also on a fixed grid (avoiding difficult neighborhoods),
- Interactions between cuts sufficiently small for local iterative OPC to converge using SMO, and
- Use of a M0 layer to reduce the number of cuts and improve uniformity of cut density.
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An algorithm was developed to resolve OPC and SMO for critical cut and hole layers:
STEP1: SMO (a.k.a. “co-optimization”) to find optimal cut shape and size, and illumination of the scanner lens entrance pupil (source) using a small representative sample portion of the layout.
STEP2: Local layout correction (pseudo-OPC) using information from Step1 to create the ideal size for the rectangles at each location: some a little smaller and some a little larger. Typically only 3 to 5 iterations are needed to reach <1 nm RMS CD for a 42nm target CD, which takes 30 to 60 seconds on a quad-core CPU, for a total simulation time of ~2 hours on a single CPU for ~120 windows.
The test chip was a 100k MOSFET, including 50 different standard cells for SRAM and logic, in 50 x 60 microns area, using a 3 x 3 microns SMO sample window. The optimal illumination was a horizontal dipole.
Complementary e-beam Lithography
Dr. David Lam, founder of Lam Research Corporation and currently chairman and CEO of Multibeam, will provide an overview of EbDW integration strategies in the TechXPOT Wednesday. EbDW can be used to “cut” the lines formed by SSDP 193i steppers so as to get the best combination of resolution and lithography-module throughput. EbDW can also be used for contact layers, perhaps using shaped apertures to make trenches instead of holes. When used to complement optical lithography, Lam calls EbDW complementary e-Beam lithography (CEBL).
Lam will discuss how CEBL plays a balancing and crucial role in meeting the industry’s patterning needs at advanced nodes, and also extends the use of current optical lithography technology, tools and infrastructure. The CEBL infrastructure exists for pitch-division tools, EbDW equipmentunder development, e-beam resists, e-beam wafer inspection, EDA tools and yield management software. This ecosystem offers a cost-effective, complete solution that scales far beyond 20nm nodes.
-Ed Korczynski