A yield optimization technique that goes beyond the traditional design-for-manufacturing (DFM) approach is one that provides greater feedback among semiconductor design, manufacturing, and testing departments. To find out more about this relatively new technique —Design for Intelligent Manufacturing or Co-Optimization — SEMICON Show Daily talked with Jean-Marie Brunet, product marketing director for model based DFM and integration to Olympus at Mentor Graphics.
SSD: Have there been any new developments on the Design for Intelligent Manufacturing or Co-Optimization front?
Brunet: We recently announced a new model for net-based critical area analysis (CAA) and scan test diagnostics that results in improved yields. We’ve worked with Samsung to develop and refine the model. This approach allows users to do a bit more yield prediction through CAA tools. In general, these tools provide a measure of the sensitivity to manufacturing defects that can increase the accuracy of yield models.
There is already that link between design flow and yield prediction. Now we are adding a link to testing to increase the predictability of a design’s sensitivity to process variability and random particle problems, which both impact yield.
SSD: Test data is being used as feedback to further improve future yields on a given product already in production?
Brunet: Exactly. That is really what we have announced with Samsung. These optimization and failure analysis tools can do a good assessment of yield and process sensitivity early in the design flow. Many IDMs use these tools at tape out and also do yield assessment based on rejects and test data that they accumulate during the manufacturing process. They collect all this data so that the knowledge can be brought back to the designer to improve the design.
Our recent announcement with Samsung provides a link to testing. I don’t mean testing as in the design for test (DFT) activities that occur during tape out. Rather, testing refers to tests on the tester, which is really a diagnostics issue. When you have rejects and faults, the traditional approach is to run many different vectors on a tester to pinpoint the source and location of the problem.
SSD: Are you linking diagnostic test to yield optimization?
Brunet: Yes. We’ve linked the test tools with certain features in the CAA portion of Calibre, e.g., the capability to use diagnostic data to trace a location on the net or bus. You may not know the exact what or why of a failure, but you can trace the failure to a particular net that can be studied from a geometric prospective to run analysis tools such as CAA or lithographic simulations. The resulting information will give us more confidence in the nature of the problem, i.e., whether it is systematic or random. Such feedback information will lead to a process or design improvement.
Designers understand the geometry. They can pinpoint a starting and an ending point on the net. On the other hand, test engineers have a more input/output (IO) perspective, that is, they know which pin is failing. To them, the chip is a black box. They cannot see inside it. Instead, they run fault simulation to reveal the problem on a particular pin of an IO interface.
What has been missing is that link between what is inside the box and what is seen externally to the box on the tester. Let’s say that you have a device under test that is functioning properly but not at speed, a problem usually attributed to a process variability issue, i.e., the design is not robust and thus very sensitive to process variability. Further, going to advanced nodes only increases the problem with process variation.
SSD: How is this information useful? How do you address the problems that you find?
Brunet: Imagine that you have a manufacturing problem caused by copper pooling, useful information that can be fed back to the manufacturer. You can pinpoint the area, explaining that you have more copper pooling on a particular net or bus than was expected. The manufacturer might acknowledge a slight manufacturing shift at that point. Or perhaps that level of pooling is normal, but not captured very well by rules. These are the types of conversations you can now have with the manufacturing fab. This is a level of interaction that never really took place before.
I don’t want to mislead you into thinking we are fixing all of the yield problems. We haven’t. Rather, this latest technology allows us to understand with much greater speed and accuracy those design portions of a net or area that are failing, which is the key concept.
– John Blyler