by Debra Vogler, Instant Insight Inc., Sunnyvale, CA
“Not only must technologies used in the electronics industry come in at the appropriate cost points, but new ways of thinking about equipment design will be needed to support the level of innovation required to do so.” That is the basic premise of the talk by Sreenivasan Koduri, TI Fellow, to be presented in his paper entitled “Packaging Manufacturing Cost: Understand It Before You Can Reign Over It,” at the TechXPOT North at SEMICON West (Tuesday, July 10, “Contemporary packaging: achieving cost advantage through innovation”).
Factors contributing to cost include pure engineering and operations costs (equipment, people, materials, etc.) as well as the cost of manufacturing technology itself (equipment productivity) (Fig. 1).
Figure 1. Typical manufacturing cost contributors. SOURCE: Texas Instruments
With respect to equipment, Koduri calls for enabling parallel mass assembly. “One of the things bringing costs down is the number of units/strip,” said Koduri. Typically, a lead frame or strip used to have about 40 to 100 or 150 units/strip. “Now, that number is dramatically changing. There are some parts that are getting close to 10,000 units/strip.” Though he could not go into specifics at this time, Koduri said that Texas Instruments is working closely with its equipment partners to implement a greater capability for parallel mass assembly. He called for an order of magnitude improvement in the scale of parallel assembly, saying “Hundreds and thousands of units should be moved simultaneously.”
Koduri also maintains that suppliers haven’t completely broken out of very traditional ways of building equipment. “Take wire bonding. We still bond one wire at a time,” said Koduri. He also pointed out that it might be time to break out of the mindset of making one type of equipment fit all applications. “Maybe there are different types of equipment needed for smaller packages vs. larger packages, or high complexity packages vs. simpler packages.”
Providing an equipment supplier’s perspective, Manish Ranjan, VP of advanced packaging and nanotechnology at Ultratech, reported that the company is seeing an aggressive transition from wire bond design to flip-chip designs on the part of its customers. The move is being driven by performance requirements and form factor considerations. “We believe that at 28nm, 75+% of leading-edge logic designs will use flip-chip packaging, and at 22nm, virtually all of these devices could utilize flip-chip packaging,” said Ranjan.
Ultratech is also seeing a transition from eutectic bump/lead-free bump into copper pillar packaging. “We’re seeing the conversion right now at 28nm in Taiwan, in the wafer foundry and OSAT market segments,” noted Ranjan. “Moving forward, I have no doubt that copper pillar will become the dominant technology solution for packaging [of leading-edge logic devices].”
In the long term, Ultratech expects that through-silicon via (TSV) solutions will have the highest growth potential. “We believe TSV high-volume manufacturing (HVM) is a few years away,” said Ranjan. “There is a lot of work now being done on TSVs by memory companies, and we believe that the initial pilot production for these devices should occur within the next 12-18 months.” The outlook for logic, said Ranjan, is that use of TSVs will probably occur at the sub-14nm technology nodes for mixed device integration (logic and memory).
Until the industry is able to do TSV at high-volume for 3D ICs, however, the use of silicon interposers – or 2.5D solutions – will have to do. Lee Smith, founder and president of Lee. J. Smith Microelectronics Industry Experts observed that Xilinx has done a significant job of developing and promoting the 2.5D architecture. But getting even this intermediate TSV-based solution to be high-volume, high-yielding and cost-effective will pose significant supply chain issues. On the technical side, Smith pointed out that the new process technologies (a high-density of fine-pitch copper pillar micro-bump on one side, and C4 bumps on the other, and some 18,000 TSVs on a 150µm-thick passive silicon interposer) required to deliver a 2.5D architecture have yet to go through their cost/yield learning curve. On the business side, one has to consider that foundries have a market price they want to get for use of the required capacity – and that they are still seeing significant demand for 65nm, 300mm services. But interposers are large, and there’s a low number of good die per wafer, so the key, said Smith, will be whether the added performance advantages outweigh the cost in the early period of the 2.5D technology deployment.