By Jeff Dorsch
For all the idle talk about “the end of Moore’s Law” (always a provocative topic, and usually wrong), there’s much more shrinkage in semiconductor dimensions to achieve. However, the question of whether it’s the end of planar processes and scaling is a matter for intelligent debate.
Technologists at Intel and various research and development organizations are looking beyond the process node of 22 nanometers to what the next step will be. Intel is moving to 14 nanometers, using field-effect transistors with fins, or FinFETs, which it calls tri-gate technology. Other leading chipmakers are less ambitious, bringing out next-generation prototypes at 20nm, 18nm or 16nm.
Lode Lauwers, imecLode Lauwers, vice president of business development at imec, says his R&D and services organization is working on FinFETs and “high-mobility materials, like germanium and silicon germanium.” He adds, “We’re working on 10 nanometers, 7 nanometers.” Interconnect and barrier materials at those dimensions represent “a very big hurdle,” he notes.
“That’s where 3DIC may come in, with much shorter interconnect, Lauwers observes. One of the biggest challenges is preparing the various wafer processing steps for those nodes, especially the lithography equipment, whether it’s extreme-ultraviolet or multiple-patterning systems. “We need to take all these items together and bring them to a certain level,” he observes.
Brian Trafas, KLA-TencorBrian Trafas, KLA-Tencor’s chief marketing officer, sees a new age in processes at hand. “For foundries, at 15 or 16 nanometers, they’re introducing FinFET,” he says. “They’re going from planar to 3D. Something similar is going on in memory, NAND, 3D structures. There will be a new set of tools, 10, 14, 16 nanometer capable, across all of our product lines,” says Trafas.
At the 28-nanometer node, integrated device manufacturers and silicon foundries introduced high-k/metal gate technology, “a process stack with CMP and etch steps,” the KLA-Tencor executive observes. “That process step was very challenging.”
Indeed. Taiwan Semiconductor Manufacturing last year had significant yield issues with 28nm designs, causing some consternation among NVIDIA, Qualcomm and other TSMC customers, who could not get all of the 28nm chips they ordered.
“HKMG provided performance advantages,” Trafas says. “We saw a lot of focus on advanced bright-field inspection systems.”
For foundries, there are “still some challenges in 28-nanometer,” he adds, while adding that there are now, worldwide, some 250,000 wafer starts per month with 28nm chips.
Twenty-nanometer ICs are “not as abrupt a change; there’s more use of double-patterning lithography,” Trafas says. “This focus on shrink has been pretty challenging with 20-nanometer.” He adds that 16nm and 14nm will be “a very challenging node, because of the introduction of FinFET.”
Risto Puhakka, president of market research firm VLSIresearch says sub-22nm processes are “moving along,” yet they create “more complex optimization.” He adds, “We see people moving ahead; they’re talking 14 nanometer, 12 nanometer.”
“The big scaling benefit is moving to FinFETs,” he notes.
Paul Lindner, executive technology director at EV Group, notes that linewidth dimensions don’t matter much when it comes to back-end wafer processing. “We don’t think the end of scaling is near,” he says. “Fully depleted planar is easier to implement than tri-gate.” When it comes to sub-22nm design and manufacturing, Lindner says, “smarter system design and 3DIC integration will benefit IC technology.”
SEMICON West will address next-generation process nodes in several forums. On the opening day of the show, Tuesday, July 9, the TechXPOT South in the South Hall of the Moscone Center will hold a session on “Leveraging Nonplanar Transistor Architectures and New Materials to Power Mobility Apps Beyond 20nm.” The program summary says, “The mobile market is driving the semiconductor industry to continue its move to transistor architectures that offer greater performance and power benefits than traditional planar architectures. There is not, however, only one way to achieve the required performance. IC manufacturers are pursuing different strategies including leveraging innovations in design rules. To continue the pace of development below 20nm, however, the industry will need to find suitable new channel materials and processes (e.g., MOCVD). This session will present various transistor architecture options below 20nm and the status of channel materials development. Additionally, inspection and metrology challenges associated with new materials will be discussed.”
On Thursday at 8 a.m. at the San Francisco Marriott Marquis, Entegris is holding its annual Yield Breakfast, with “Defect Reduction in the Sun-20nm Era” as its theme. The program summary reads, “The sub-20nm node is marked by skyrocketing capital expenditures, adoption of difficult process technologies such as double patterning and FinFET structure, and an ever-increasing number of process steps. Yield is not only a challenge, but a key lever to the overall semiconductor business model. In this Entegris-sponsored forum, we will explore the key yield challenges and defect reduction approaches at sub-20nm nodes from three points of view – equipment, process and materials.”
The session will include a keynote address and presentations by several industry executives, followed by a panel discussion by the speakers.
The semiconductor industry is prepared to boldly go into the sub-22-nanometer era. The technical challenges it will encounter remain to be solved.