As consumer demands continue to drive increased chip performance, the semiconductor industry is abuzz with the possibilities of 3D IC integration. Qualcomm Inc., looking from the point of view of a mobile wireless company, sees significant potential in 3D IC architectures, developing some exciting new applications that are perfectly suited to the benefits of high-density chip stacking.
Matt Nowak, senior director of advanced technology, QualcommAt the opening keynote yesterday morning for the Advanced Semiconductor Manufacturing Conference (ASMC), held at the Marriott Marquis in conjunction with SEMICON West, Matt Nowak, senior director of advanced technology for Qualcomm, showed audience members increased smart phone functionality in the form of “augmented reality.” This technology that Qualcomm is working on uses a smart phone to take a picture of a scene, which the user can then click on to get more information about local restaurants, entertainment and more.
Citing a market forecast from Yole Développement, with 3D integration becoming a multibillion-dollar wafer market by 2013, Nowak said that smart phones and smart books represent one of the fastest growing application segments for 3D. “These devices are always on and always connected, and location-aware at all times.” Augmented reality is a “very interesting application for high-density through-silicon stacking,” Nowak added, noting its need for very high bandwidth and functionality in a very small form factor.
3D integration comes in any number of sizes and flavors, each with its own set of challenges and opportunities. Monolithic integration is still in the research phase, but there are various forms of stacked ICs that are currently in production. Package on package (PoP) and package in package (PiP) are being produced in high volumes, as is bare die stacking without through-silicon vias (TSVs), Nowak said.
Bare chips with TSVs are not yet in volume production, but show considerable potential. High-density through-silicon stacking (TSS) was the focus of Nowak’s keynote discussion. The technology uses small-diameter (~ 5 µm), high-aspect-ratio (~10:1) TSVs; a via-middle process flow, with the TSV being formed after FEOL; backside wafer interconnect processing; high-density tier-to-tier microbump connections; thousands of TSVs and microbumps per chip; and includes design and test enablement, tools, and methodologies.
Probably the biggest motivation for the technology is that it enables architectural innovation, Nowak said. “If you can do it with wire bond, you probably should because it’s going to be cheaper,” he said. “But this technology can be very differentiating.”
Over the past year or so, high-density through-silicon stacking has gathered a lot of momentum, and particular work has gone into design strategies and methodologies, Nowak said. But of course the technology is not without its challenges. There’s no consensus for standard manufacturing flows, yield and reliability are not proven, there’s a lack of consensus with regard to cost targets, and the industry is yet to decide who will do what in the supply chain, he said. The ecosystem needs to be established; and process flows, roadmaps and fundamental standards need to be put in place. “We need to figure out where we’re going.”
Packaging expert Phil Garrou, in an October blog for Semiconductor International, likened the challenges facing 3D integration to the Four Horsemen of the Apocalypse, identifying them as manufacturing cost, test, thermal management and design. “We’re well on the way to taming these beasts,” Nowak said.
There are several cost contributors for manufacturing, including the silicon area for TSVs (you can’t put circuits where you put the vias), incremental test cost, TSV and microbump yield loss, and incremental TSS process steps. But there are also several opportunities for cost savings, Nowak said, pointing to variability in the laminate package size and number of layers, and the ability to split a very large die into two higher-yielding die, split a die into heterogeneous technology nodes, and aggregate metal layers to reduce the total number. All of these are very dependent on the application, however, he added.
For the TSS high-volume manufacturing process, cost is very dependent on materials, which make up 44% of the cost in one example Nowak showed. So significant cost savings could be introduced through material innovations. Equipment cost-of-ownership (CoO) improvements could figure prominently as well, since equipment depreciation accounted for 27% of the cost.
The next important step for TSS, Nowak said, is to start putting standards in place for the technology, including standards for EDA tool data formats, design for test (DFT), stackable die interfaces, metallurgies, shipping carriers/transport of thinned wafers, temporary carriers and handling of thin wafers, ESD protection, reliability criteria, quality assurance specifications, and non-destructive metrology. “The through-silicon stacking ecosystem and standards need development,” he said.
SEMI and Sematech are partnering on a workshop today at 1 p.m. at the Mariott Marquis, titled, “3D Interconnect Challenges and Need for Standards,” moderated by Urmi Ray, a senior member of the technical staff at Qualcomm.
— Aaron Hand, SEMICON West Daily News