With the potential to address the rising demand for smaller, more functional, and lower-power chips, 3D architecture is emerging as a prime candidate for meeting leading-edge chip requirements. Through-silicon vias (TSVs) appear to be a viable solution. Indeed, industry interest in emerging 3D TSV technology has grown, given its adaptability to both die-to-die and wafer-to-wafer stacking. The TSV approach merges the performance and functionality of system-on-chip (SoC) architecture with the functionality, cost and time-to-market advantages of system-in-package (SiP).
Among the key processing steps that enable 3D integration are alignment and bonding, which allow for the interlayer connection of TSVs that provide the electrical interconnects. Wafer-to-wafer (WtW) and die-to-wafer (DtW) bonding is key to the 3D interconnection of wafers by stacking. Precise alignment is one of the major challenges affecting the performance of 3D interconnects.
The first metrology challenge starts when the wafers are bonded. In wafer-to-wafer bonding, pre-bond inspection is critical to ensure the proper interconnect alignment. If the bonded wafer pair is misaligned or if the overlay is insufficient, the bonding quality can be compromised. Therefore, it is important to analyze all the contributing factors to the alignment accuracy.
IR microscopy can be used to measure the overlay accuracy of the bonded wafer pairs required for 3D interconnects.Infrared (IR) microscopy is a non-destructive, in-line metrology technique that can be used to measure the overlay accuracy of the bonded wafer pairs required for 3D interconnects. It is a method capable of “seeing” through the silicon, which enables a variety of metrology techniques, including the calculation of overlay error. IR can measure the overlay error in bonded wafer pairs immediately after the pair leaves the bonder. As a result, overlay can be quantified and compared to design overlay tolerances, and decisions can be made on whether to continue the processing steps to complete the 3D integration.
However, measuring opaque films and the high-aspect-ratio features that dominate 3D architectures still poses some challenges. Metrology for 3D architectures requires new techniques, revisiting and improving some older techniques, and breakthrough innovations to create new metrology tools.
To gain a better understanding of how new and existing wafer metrology technologies can be used, modified or enhanced to measure and improve 3D interconnect processes, Sematech is hosting a 3D Metrology Workshop on Wednesday at 1 p.m. at the Marriott Marquis, in conjunction with SEMICON West.
To identify critical issues and gaps, technology timing, and key process specifications, a collaborative, industry-wide approach must be adopted to develop and implement solutions for making critical, next-generation interconnects manufacturable. Sematech’s 3D Interconnect program has made a case for TSV’s commercial viability, and has been investigating the integration of both die-to-wafer and wafer-to-wafer 3D technologies, including process development, TSV reactive ion etch, wafer bonding, wafer thinning, die bonding, TSV metallization, and accompanying metrology techniques.
— Sitaram Arkalgud, Director of 3D Interconnect, Sematech