by Debra Vogler, Instant Insight Inc., Sunnyvale, CA

The decision to use stacked die or TSV-enabled devices is intertwined with cost considerations – there are no surprises on that point. However, Risto Puhakka, president, VLSI Research, emphasizes that the decision to go to 3D packaging is a technology play, not a cost play. No matter how demanding companies are in their insistence on lowering the cost of 3D packaging, it will still cost more than today’s packaging solutions. “The challenge is how to get more money out of the device/package,” said Puhakka.

VLSI Research believes that implementation of 3D packaging will happen in the areas where there’s enough bang for the buck. “It probably lends itself to very high-end server applications, and maybe some high-end mobile,” said Puhakka. “But mainstream PC or mainstream tablet – no way!” Well, at least not for a while. Because of the cost sensitivity of the memory segment, Puhakka thinks the industry will likely see only some 3D memory applications in either late 2012, or in 2013, and in very narrow segments at that. “The DRAM production year is 2012, but there will only be a 10% market penetration by 2016,” said Puhakka (Fig. 1). “For processors, we expect production in 2014 and by 2016, 25% will be using it.” Testing 3D devices is often considered to be a very big challenge, but Puhakka sees no roadblocks there. “We don’t see any problem on the horizon, and the EDA companies are addressing the issues.”

Figure 1. Where TSVs are emergent (dated 2012). Source: VLSI Research

E. Jan Vardaman, president and founder of TechSearch International, observes that while the drivers for 3D TSV remain constant, the timeline for its adoption keeps shifting out. A key to this technology entering high-volume manufacturing (HVM) is resolving the technical and business issues. “One of the main technical issues is in the wafer thinning process, specifically the debond step,” noted Vardaman. “Several companies are developing new materials that may improve yield and new equipment may also be introduced in the future.”

Vardaman also pointed out that the “known good die” methodology is a requirement to provide high enough yield to make TSV processes cost-effective. “Companies are still discussing issues such as whether to probe or not to probe wafers, the use of built-in self-test (BIST), and required test methodologies,” said Vardaman. “Until all issues are resolved with 3D TSV, alternatives including stacked die, chip-on-chip (CoC), and package-on-package (PoP) will flourish.” TechSearch International’s data indicates that 600 million PoPs shipped in 2011, and the number is expected to increase over the next few years. “Recent extensions to PoP, including ultra-thin embedded die PoP that can deliver a total package thickness below 1mm will extend the life of PoP.”

Steve Pateras, product marketing director for design-for-test (DfT) at Mentor Graphics, explained that the ability to enable comprehensive testing of all popular DRAMs and related TSV-based buses, and being able to generate high-quality tests for logic-on-logic stacks, were key challenges. The company’s Tessent platform addresses these issues by using a combination of hierarchical test architecture, high-compression scan testing, and BIST technologies. Making the case for BIST, Pateras observed that there is a dual value in adopting it for 3D ICs. “You get more efficient wafer sort testing, and those same resources can be used for retesting within the stack,” said Pateras.

Wafer sort testing also has to be much better when going to 3D-ICs. Testing of high-speed I/O, for example, is particularly challenging if done by making physical contact (resulting in physical damage upon touchdown, or physical space limitations). Fixturing at the wafer-scale level can also have performance issues related to reflection and inductance, making it difficult to get high-speed accuracy. To address these problems, Mentor uses contact-less solutions whereby delay-based measurements can be done.

by Debra Vogler, Instant Insight Inc., Sunnyvale, CA

With Intel already ramping its 22nm manufacturing process into high volume using its third-generation high-k metal gate and Tri-gate (fully-depleted) transistors, the company is advancing its Atom processor roadmap at twice the rate of Moore’s Law through 2014. In a pre-SEMICON West interview, Kaizad Mistry, Intel’s VP of logic technology integration, told SEMI that the company will be extending its Tri-gate to 14nm, with a second generation fin-based architecture.

How will the rest of the industry fare with the introduction of 3D transistors? The point at which leading-edge IC manufacturers move to 3D will be different for each one, and will depend on each company’s specific product offerings and applications. “From a bulk perspective, the industry is starting to move into a tri-gate and FinFET-based structure,” said Raj Jammy, VP of materials and emerging technologies, SEMATECH. “The folks who continue to use SOI-based technology enjoy an advantage in that they can scale on SOI for a little while longer, but eventually, the expectation is that everyone will have to move to a 3D device.”

Steve Longoria, SVP of business development at Soitec, makes the case for the evolutionary path to a 3D transistor architecture, which will probably have to be made by everyone at the 14nm node (Fig. 1). He views the SOI-based technology as a bridge for the industry. By starting with a fully-depleted planar transistor on an SOI wafer at 28nm (using Soitec’s FD-2D wafer, which STMicroelectronics has done), the industry can get the power and performance benefits of a fully-depleted transistor. Then, once the industry is ready to implement 3D ICs at 14nm, the company’s FD-3D wafer would come into play. “The FD-3D pre-defines the fin height, and the buried oxide layer provides built-in intrinsic isolation,” explained Longoria.

 Figure 1. The Soitec roadmap. SOURCE: Soitec 

While the microprocessor manufacturers make their choices about which path to take to get to 3D ICs and when to make the jump, memory manufacturers also have some scaling choices to consider – but here, “3D” includes the packaging technology. “We see DRAM extendibility until probably 2020, and then after 2020, we think we’ll probably see the spin torque transfer MRAM come in,” noted Mark Thirsk, managing parter, Linx Consulting. “But the big transition between now and then is 3D (TSV-based) packaging technology,” which he views as taking up the slack in DRAM scaling.

Thirsk maintains that NAND will be more difficult. “Does NAND go 3D and stay with a floating gate structure, or do we add in a charge trap approach – or do we go to something that looks like a resistive or ferroelectric approach?” mused Thirsk. He believes that this competitive NAND technology challenge has to be solved in the next two or three iterations of NAND. “So in the next two-to-four years, we need to be quite clear on what the next-generation is, and I don’t think that clarity exists today.”

Adding to the uncertainty is that early work on charge trapping shows it doesn’t solve all the problems. And floating-gate technology in 3D, while probably a first approach, will be difficult because 3D is quite difficult to stack. “The ITRS, in the very far-out years, is calling for 128 layers for the most advanced devices,” observed Thirsk. “Most people we’ve talked to say that’s a pipe dream – it can’t happen.” He speculates that the limit on stacked layers is probably in the range of 32 to 64. “Again, 3D packaging (TSVs) will be needed to help in 3D NAND.”

by Debra Vogler, Instant Insight Inc., Sunnyvale, CA

The announcement of EV Group’s 450mm patterned wafer at last year’s SEMICON West unleashed even louder debate on the economic need for 450mm manufacturing. With more equipment suppliers announcing 450mm efforts, and a long list of research consortia dedicated to developing 450mm, it does seem as though the industry is clearly aiming for the finish line. While some are providing definite commitment dates, there are also those issuing words of caution.

Suppliers on the 450mm Bandwagon

Thomas Glinsner, director, product management, at EV Group, reports that the company is part of a number of European-funded projects (see Fig. 1) including: EEMI450, SOI450, NGC450, and EEM450PR. Still another project – in the discussion phase as of this writing – is KET-Eol.

Figure 1. Overview of European funded R&D projects (450mm). SOURCE: EEMI450 Initiative 

The company still stands by its estimate for 450mm HVM insertion as somewhere between 2015 and 2017. Realizing that there will be a much smaller number of end users for 450mm manufacturing, “EVG wants to be ready for 450mm processing as soon as the foundries and IDMs are ready to make the transition,” said Glinsner. In fact, the company wants to be early in the game. “That’s why we’ve developed the 850SOI bonding system. SOI wafers might play a big role beyond 20nm, and we want to be a part of that, so we decided that this would be the first equipment we would build on a 450mm platform.”

Ultratech is also enabling 450mm manufacturing by working with SEMATECH and with large IDMs and foundries to understand the timelines. “Ultratech’s position is that it will have the equipment available to transition to 450mm,” noted Scott Zafiropoulo, VP of marketing at Ultratech. The company is using a two-phase approach to develop 450mm tools for both packaging and laser spike annealing applications. For either product development effort, the company will first scale-up the tool itself, and once proven, the second phase will tackle productivity improvements.

According to Manish Ranjan, VP of advanced packaging and nanotechnology at Ultratech, the company’s efforts to scale up its Unity AP300 tool to 450mm will begin with the wafer stage and mechanical scaling during phase one. Phase two will focus on increasing throughput with a new lens design and a different optics configuration, among other changes. “Taking a two-phase approach enables us to minimize risk and meet the time-to-market requirements of our customers,” said Ranjan.

To scale up Ultratech’s laser spike anneal (LSA) technology for 450mm, the first phase of development will include the wafer handling and the stage, explained Jeff Hebb, VP of laser product. This first phase should be done in late 2013, based on the G450 Consortium timeline. Phase two of the effort would be scaling the optics to improve productivity, which could include making the beam 2x longer, or perhaps even using a new laser, or significantly changing the optics. “But there are no technical showstoppers,” stated Hebb. By working on the optics in parallel with the phase one efforts, the company can avoid risking the 2013 date by not including optics redesign or new laser selection in the first phase.

The Experts’ Take on 450mm

Gartner’s analysis indicates that the first production fabs will be ready by 2018 (plus or minus two years) (See Fig. 2). “It’s contingent on lithography being ready,” said Dean Freeman, research VP at Gartner. Laying out a general timeline, Freeman figures that the industry could have pilot line tools shipping in 2013 – with all of them getting into fabs by the end of that year. “Then you’ll probably see beta tools start to emerge in 2014 and 2015.” He added that if the beta tools are good enough to go into pilot line production, there might be pilot lines in the late 2014/2015 timeframe. It might take another two years to wring out the costs and fine-tune the systems, so Freeman projects that the earliest the industry might see production is 2017/2018 – unless efforts are accelerated.

Figure 2. 450mm implementation timelines (dated May 2012). SOURCE: Gartner 

Further complications arise if EUV isn’t ready by the time 450mm really comes into play sometime between 10nm and 8nm, noted Freeman. As a result of a delay in EUV, with the attendant costs associated with more patterning steps, there is a possibility that the transition to the next technology node might be slowed. Even at 20nm, Freeman observed that the fabless sector is complaining that the performance/cost ratio is not what has been seen in the past. “Where normally it would be a 28% improvement for a 20-30% better performance, now, we may not see either the performance or cost improvement [for 450mm]. We’re such a cost-sensitive industry that IC manufacturers will look very closely before pulling the trigger on a 450mm fab going forward.”

Adding to the uncertainty is the actual R&D tab for 450mm. “All we have are estimates,” comments Bob Johnson, research VP, at Gartner. “We think the estimate of $15B to $17B for 450mm R&D costs is fairly good.” He also mentioned that SEMI estimates have been as high as $25B to $40B. Noting the importance of obtaining data from alpha tools and subjecting 450mm wafers to “real” processing conditions, Johnson calls the work that the G450 Consortium is doing “absolutely critical.”

Aside from whether or not EUVL will be ready in time for the 450mm transition, there is also a concern about materials development for more advanced (sub-14nm) nodes. “It would probably be too much to bite off and chew to address fundamental materials science challenges and an entire new equipment platform at the same time,” observed Paul Kirsch, director of front-end processes at SEMATECH. “It’s not completely clear how the materials roadmap merges with the 450mm roadmap.” He suggested that it might be more prudent to address fundamental issues with processes, such as CMP and etching, on more mature equipment.

Whatever the worries concerning R&D funding, EUVL delays, or critical materials research, the select group of IC manufacturers and foundries that have the wherewithal are moving forward with 450mm. TSMC’s senior director, 450mm program, C. S. Yoo, explained that the company is engaged with tool suppliers to address the challenges of 450mm manufacturing. “These challenges include tool throughput, cost, and performance,” said Yoo. “We’ve played an active role to support industry efforts to create standards for 450mm production in the Global 450mm Consortium.” Yoo also said that the company plans to set up its own 450mm module line starting in 2014, with volume production after 2016 (Fig. 3).

Figure 3. TSMC’s Fab 12 GIGAFAB located in Hsinchu, Taiwan. The Company’s Phase 7 expansion will incorporate technology for the planned production of 450mm wafers beginning after 2016.

Acknowledgment

GIGAFAB is a trademark of TSMC.

by Michele Chandler

At the opening keynote of the SEMICON West 2012 exhibition in San Francisco, Shekhar Borkar, Intel Fellow and Director of Extreme-Scale Technologies at Intel Corp., detailed research efforts to develop a new generation of computing systems. Borkar’s speech, “Ubiquitous Computing in the Coming Years — Technology Challenges and Opportunities,” described his research efforts to create new technologies which enable computers to work ever faster while consuming far less energy.

As they exist today, microprocessors do not carry very high energy efficiency, Borkar said. “But the next class, digital signal processors, have by two orders of magnitude better energy efficiency than general processors.”

Raising performance while cutting energy use has wide applications, from military uses to more powerful consumer devices.

“Think about a 20-watt petascale machine in Iraq. A petascale machine today is about as big as this room,” Borkar explained. But shrink it down so it fits on an airplane, he explained, and “now you can have a terascale machine sitting in the backpack of a solider. Or think about a terascale machine sitting in your laptop.”

He added, “What you see is from gigascale to terascale, the performance of the processors increased by 30X. From gigascale to petascale, the performance leapt by 250X. The system level performance increased faster than the transistor level performance or the processor level performance.”

Borkar then shifted gears to discuss upcoming advances in storage technology, which presently includes SRAMs, DRAMs, NANDs, PCMs and Disks, with SRAM semiconductor memory currently recognized as the most energy-efficient.

Borkar, who served as the principal investigator of the Ubiquitous High-Performing Computer project, an initiative funded by DARPA, the research arm of the U.S. Department of Defense, said, “I expect the future systems to have SRAMS, DRAMS…as well as some disks.” Borkar said. “So, the DRAM is here to stay.”

by Jeff Dorsch

The era of 3D integration calls for greater collaboration among fabless semiconductor companies, silicon foundries and the silicon supply chain, according to Ivo Bolsens, senior vice president and chief technology officer of Xilinx.

Giving Wednesday’s keynote address, titled “All Programmable – From Silicon to System,” Bolsens said his company’s collaboration in supporting today’s 3D devices with silicon interposers and advanced packaging stretches back to 2006. In 2008, Xilinx began meeting with suppliers of silicon equipment to learn about manufacturing capabilities firsthand. After that, it turned to Taiwan Semiconductor Manufacturing and other foundries to discuss the process issues involved, he noted.

“It was almost a science project,” Bolsens recalled, as Xilinx held meetings with suppliers of semiconductor materials and packaging to gather greater understanding of all the aspects that go into producing a 3D chip. The product introduction finally came last year.

“The supply chain clearly has changed in the last few years,” he said. “Three-D is driving that. We are broadening our touch points in the supply chain.”

As one of the world’s leading suppliers of field-programmable gate arrays, Xilinx has to “bridge a pretty big gap between the system houses and our suppliers,” Bolsens noted. Xilinx has Ericsson and other system manufacturers among its customers, and “we talk to our customers about the value we bring to them,” he added.

Collaborating with companies in the supply chain and among foundries is “definitely a win-win situation,” the Xilinx executive asserted. Establishing a continuous, early feedback loop with the foundry as the first 3D chips went through their wafer fab was key to identifying IC defects and correcting them in short order, he said.

“A chip is as good as its weakest link,” Bolsens observed.

To meet the challenges of cost reduction, design support and scalability, Xilinx and other fabless companies are looking to electronic design automation vendors to help resolve a number of issues, he said. “The EDA industry has to come to the rescue,” he added.

In conclusion, 3D integration poses a number of challenges, according to Bolsens. “The cost has to go down. The industry has to agree on scalability,” he said. “There’s a lot ahead of us.”

by Jeff Dorsch

“It’s been a very difficult time to be in the solar industry,” acknowledged James Brown, executive vice president of global business development at First Solar, in his Wednesday keynote address for the Intersolar North America conference.

Taking “Solar Power’s Transition from Subsidy Dependence to Mainstream Energy Solution” as his theme, Brown said this year has been marked by “a lot of pain” and “chaos” for those in the solar industry. “We had become over-reliant on the subsidies,” he noted, many of which are being reduced or eliminated by governments around the world. In this “false and protected environment,” the solar industry didn’t really have to compete with the fossil-fuel industry, and it now finds itself having to contend with a variety of energy sources, Brown said.

“The good news is it’s not all gloom and doom,” the First Solar executive asserted. There are “long-term opportunities” to be found, especially in the area of energy security, he added.

“Emerging and fast-growing economies need power quickly,” Brown said. “Solar is the best way to get power to the 1.5 billion to 2 billion people who don’t have access to power.”

He urged industry participants in the audience to “get those ideas off the whiteboard and into practice. Solar is becoming part of the energy mix. Our industry will likely need to go through a number of evolutions in the next few years.”

He closed with a quotation from Peter Drucker: “The best way to predict the future is to create it.”

The questions we hear from mid-end production folks concerned with package-related device reliability at the wafer level often sound like this —

    • We’ve had some interconnect issues on diced die. Can we look at them at the wafer level before dicing?

    • Can we find out how consistent our MEMS cavity seals are?

Sonoscan’s twin-transducer high-throughput AW300™ automated wafer scanner scans two 300mm wafers at a time. Or two 200mm wafers. Or two 150mm wafers.

Its wafer-handling robot can accept various types of wafer carriers and precisely positions each for scanning.

The two ultrasonic transducers each scan a wafer at high speed and high ultrasonic frequency (= high resolution). Gap-type defects (meaning non-bonds, delaminations, voids and cracks) are reported by their exact location, which permits their later removal after dicing.

Gap-type defects can occur in 3D IC, chip on wafer, chip stack on wafer, direct bonded wafers, anodic bonded wafers, and intermediate bonded wafers.

Even very tiny defects cannot escape detection. Of all possible internal features, gap-type defects reflect ultrasound most strongly, and therefore send back the strongest return echo signals.

Have a question of your own? Send it to Sonoscan’s expert, Ben Liu at [email protected]

by Steve Buehler

What’s driving the semiconductor manufacturing industry today? To a large extent, it’s the rise in mobile computing- smartphones, tablets, and ultra-portable notebook PCs. If you’re addicted to your Apple iPad, or you can’t put down your Samsung smartphone, then you’ll love the new SEMICON West mobile app for attendees, which brings virtually all of the show content to iPhones, iPads, and Android devices. The SEMICON West mobile app, sponsored by Applied Materials, acts as a portable guide to the event, with access to complete exhibitor listings, floor plans, program schedules, speakers, and local information. The new app is available now from the iTunes Store and Google Play.  More information about the app is available at: www.semiconwest.org/Participate/MobileApp.

And what’s the biggest wafer issue at West this year? Of course, it’s the industry transition to 450mm wafers. Will anyone spend the billions of dollars necessary to bring these super-sized silicon discs into high-volume manufacturing, or will there be a lot of talk and very little productive development for the few tools that will be sold into a very small number of fabs? The SEMICON West 450mm Supply Chain Forum and the 450mm Standards events will be where everyone hopes to discern reality from rhetoric.

On the other hand, the smallest issue is the ongoing shrink of half-pitch dimensions. SEMICON West has Sub-22nm and EUVL forums where you can find out just how everyone – or maybe only a few – will get down to 20nm and 14nm nodes. If going vertical is your thing, there are 3D seminars that will focus on FinFETs, 3D-capable SOI wafers, and the advanced techniques to make this all work.

The SEMICON West 2012 “Extreme Electronics” Exhibits and Presentations will focus on Manufacturing Technologies for the Growing Microelectronics Technology Markets.

Speakers from Cree, Seoul Semiconductor, Micralyne, InvenSense, Hanking, Panasonic and more will discuss the latest manufacturing and technology trends at SEMICON West 2012, in the Extreme Electronics “show-within-the-show” exhibit area.  The co-location of LED, MEMS, and plastic electronics-focused exhibitors within the SEMICON West exhibition shows the synergies between semiconductors and related adjacent markets.

And Moore! And More! And Moore! And More!

Also at the SEMICON West 2012 exhibition:

MEMS: Taking MEMS to the Next Level: Transitioning to a Profitable High-Volume Business on Tuesday, July 10, 10:30am–3:30pm, with speakers from InvenSense, Yole Développement, Hillcrest Labs, Coventor, Hanking Electronics, Micralyne, Applied Materials, Nikon, ScanNano, NIST and more.

LEDs/Solid State Lighting: Enabling the Next-Generation of HB-LEDs on Wednesday, July 11, 10:30am–3:30pm, with speakers from Cree, Soraa, Everlight Electronics, EV Group, Canaccord Genuity, LayTec AG, Seoul Semiconductor, Lattice Power, Yole Développement, GT Advanced Technologies and more.

Plastic/Printed Electronics: Practical Plastic Electronics: Bringing Disruptive Flexible and Organic Materials into Volume Electronics Manufacturing, on Thursday, July 12, 10:30am–1:00pm, with speakers from IMEC, Panasonic, DisplaySearch, Imprint Energy, Applied Materials, and MC 10.

Focus on TechXPOTs

And finally – the SEMICON West TechXPOTs are the place to hear about the latest technology developments and breakthroughs in semiconductor manufacturing. From presentations on cutting-edge materials, to the latest news on next-generation lithography, 450mm, and other major industry initiatives, the TechXPOTs are the place to find out what’s new and what’s next in microelectronics.

   South Hall

Tuesday, July 10

10:30am-12:30pm       Enabling Sub-22nm with New Materials and Processes

1:30pm-3:30pm           A Look to the Next Generation of Electronic Materials

                                     Hosted by the Chemical & Gases Manufacturer Group (CGMG) of SEMI

Wednesday, July 11

10:30am-12:50pm       Lithography: Extending Double-patterning, Industrializing EUV and Complementary Technologies

1:30pm-3:30pm           Secondary Market Challenges and the Future

     Hosted by the Secondary Equipment and Applications Americas Chapter

Thursday, July 12 

10:30am-12:00pm       SEMICON West 450mm Supply Chain Forum

1:00pm-3:30pm           ITRS Front End of Line Technologies

 North Hall

Tuesday, July 10

10:30am-12:30pm       Contemporary Packaging: Achieving Cost Advantage Through Innovation

    Hosted by the Advanced Packaging Committee, SEMI Americas

1:30pm-4:00pm           Semiconductor Test: Adding Value through Yield and Better Data Management

Wednesday, July 11

10:30am-12:30pm       Highlights of International Test Conference

1:00pm-3:30pm           The 2.5 & 3D Packaging Landscape for 2015 & Beyond

    Hosted by the Advanced Packaging Committee, SEMI Americas

Thursday, July 12

10:30am-12:30pm       MEMS and Sensor Packaging

    Hosted by the Advanced Packaging Committee, SEMI Americas

1:00pm-3:30pm           ITRS Back End of Line Technologies