by Debra Vogler, Instant Insight Inc., Sunnyvale, CA

Though industry experts can debate which is the better transistor architecture solution (non-planar or ultra-thin SOI) to control short-channel effects and leakage on the path to sub-14nm technology, there is no debate that new channel materials will be needed. Paul Kirsch, director of front end processes at SEMATECH, expects germanium (Ge) to enter the roadmap first as an enhancement for pMOS FETs in a non-planar architecture. Because III-V materials are more challenging to integrate, Kirsch expects those will come into play most likely beyond the 10nm node. “Depending on the success of our development efforts, you could see the presence of some Ge at 14nm as a channel material, but it’s unclear at this time if it would take the form of SiGe or a pure Ge material,” said Kirsch. “Both are possibilities at 14nm.”

A major challenge is developing a low-cost process technology to deposit III-Vs and Ge on top of silicon. “Ge process technology has progressed nicely because SiGe is already used for a source/drain stressor material,” observed Kirsch. “So the issue isn’t so much with Ge but with III-V molecular beam epitaxy (MBE).” MBE requires expensive tools and specialized operators and uses a lot of expensive consumables, Kirsch noted. And, he added, the throughput is not high. Because of these drawbacks, he believes that metal organic chemical vapor deposition (MOCVD) might be required for III-V high-volume manufacturing (HVM) on a silicon substrate.

As with just about every new process or material integration effort, implementing MOCVD is not going to be easy. Kirsch cites the lack of 300mm tools suitable for HVM MOCVD (only beta versions are in development), the difficulties in handling the materials, and the environment, safety, and health (ESH) issues. Defectivity is also problematic. “Silicon and SOI substrates have very low defect densities – probably below 1000 or even below 100 defects/cm²,” said Kirsch. “But III-V is typically closer to 1×108 defects/cm², so growing a film with a lower defect density and engineering the process equipment to enable that lower defect density are key challenges.

The monitoring and control of new processes developed for new materials will also pose challenges for metrology suppliers. Lanny Mihardja, product marketing manager, FaST division at KLA-Tencor, reported that the company’s customers are in the process of characterizing blank film stacks for III-Vs and Ge with respect to optical properties. “As time goes on, they will start looking at how they want to shape and design the composition of these materials [III-Vs and Ge] into their structures, and eventually, deciding how these new gates will be formed.” Even if 3D structures and shapes are not yet available, evaluating the blank film stacks is difficult enough because a multiple film stack has to be measured to be able to deduce the optical properties, thicknesses, and indices of refraction – all prerequisites to being able to tackle the shape and CD measurements.

Aside from the technical challenges associated with the growing importance of new materials at 14nm and below to support deposition processes, including patterning technologies, there is the market potential to consider. Mark Thirsk, managing partner at Linx Consulting, believes that the market for advanced materials will grow faster than the semiconductor device market (Fig. 1). “In 2012, advanced materials are just under 2% of the total cost of semiconductor revenue,” said Thirsk. “By 2020, we think that will be closer to 3.5-4%.”

Figure 1. Process materials requirement as a percentage of semiconductor revenue. SOURCES: Linx Consulting, IC Knowledge

by Debra Vogler, Instant Insight Inc.

Making good on its 22nm Tri-gate announcement last year, Intel is already ramping to high volume with its 3D (fully-depleted) transistor architecture. Among the benefits are a reported 37% performance increase at low voltage and >50% power reduction at constant performance. In a pre-SEMICON West interview, Kaizad Mistry, VP, director of logic technology integration at Intel said the company plans to extend its Tri-gate technology to 14nm. Thus, the race to get below 22nm is already in progress.

There is another camp, however, that suggests it would be better for IC manufacturers to not make the leap to both a 3D structure and fully-depleted transistors in one step, as Intel has done. “At 28nm, the industry is already struggling with managing leakage and driving yields,” observed Steve Longoria, SVP, business development at Soitec. “So this is a red flag on the field of our industry and it will be even worse at 20nm. Many companies are questioning if they should even do a bulk CMOS solution at 20nm.”

By using silicon-on-insulator (SOI)-based technology as a “bridge,” the industry can get the performance benefits of a fully-depleted transistor while staying with a planar transistor at 28nm and down to 14nm (or sub-14nm), when some sort of FinFET or tri-gate type of structure will likely be required. “With a fully-depleted planar architecture, you can take advantage of the power performance jump,” said Longoria. He noted that STMicroelectronics’ decision to go with SOI-based technology [the FD-2D wafer] at 28nm enables a 40% power performance bump over bulk silicon. “The fully-depleted two-dimensional solution enables a more regular migration for the industry,” meaning that it’s not a huge leap for the foundries and the design ecosystem/EDA/IP sectors. “One can stay with the same manufacturing process, same manufacturing tooling, same design flow, and same IP.”

Soitec’s solution for when the industry must move to a FinFET or tri-gate type structure is the FD-3D SOI wafer, which pre-integrates critical characteristics of the transistor within the wafer structure. For its FD-3D wafers, explained Longoria, “We’ve preset the height of the fin at the wafer layer and taken out significant front-end process steps that more than outweigh the cost adder of the wafer.” (Fig. 1). “Because we have this buried oxide under the fin, where we’ve fixed the height, you no longer have to do all your isolation processes between fins (such as STI and high-energy implant under the fin).”

Figure 1. A Fin-first process on FD-3D. SOURCE: Soitec

Longoria added that if the industry can reduce a few mask sets and do pre-processing, it’s a huge cost savings. “It’s moving some of the complexity out of the foundry and into the wafer manufacturer to result in a lower cost system-on-chip (SoC),” said Longoria. He also observed that if a company were to start today and try to implement a FinFET process, the estimate from companies such as IBM is that it would take 5 to 7 quarters less development time using the SOI wafer because of the steps that don’t have to be developed. Longoria pointed out that IBM is committed to using SOI for its FinFET offering starting at 14nm, including server processors and ASICs. Among the benefits of FD-3D technology that he says are important to IBM are the reduced process complexity, which offsets the wafer cost, and a better soft-error rate immunity. Between its two SOI-based solutions, Longoria says there is an early, low-risk migration at the 28nm down to 10nm and beyond.

Looking ahead, Soitec will be adding strained silicon to both its FD-2D and FD-3D product lines, with preproduction expected no later than 2014. Beyond the 14nm node, the company is also researching the use of Ge or III-V materials, as well as new transistor architectures, such as nanowires. Longoria said the company’s technology is fully scalable to 450mm wafers, and it will be ready well ahead of the industry’s need, though as of this writing, 450mm sample wafers have not yet been made available.

Equipment suppliers getting ready for sub-2Xnm

Two critical processes needed for making transistors are implantation and annealing. Applied Materials launched its latest Applied Varian VIISta Trident high-current implantation solution a few weeks before SEMICON West. Targeting sub-2Xnm transistors, the company believes that the horizontal and vertical angle control feature on the new implanter will be important for 3D transistor manufacturing, though Tom Parrill, high-current marketing director at Applied, said the company could not discuss applications of the tool for 3D transistors at this time. Going forward, Parrill said that the new system – based on proven ribbon beam design technology – is believed to scale very well to 450mm wafers.

Ultratech’s laser spike-annealing (LSA) technology is being developed for 20nm as well as sub-20nm nodes. “For the foundry market, it’s still planar transistors,” explained Jeff Hebb, VP of laser product at the company. “No one is going to FinFET or 3D structures [the foundries] at 20nm as far as we know.” Therefore, traditional users of advanced annealing, such as LSA, still need to activate dopants at 20nm, he explained. And though Hebb doesn’t expect to see more junction activation steps in going from 28nm to 20nm, he says there is a trend to do more non-junction activation steps where either millisecond annealing or LSA is being used.

Ultratech is already working with its customers to use LSA to improve the device performance of FinFETs (Fig. 2). “We see no showstoppers to apply LSA to FinFETs,” noted Hebb. “In fact, our advantages (minimal pattern loading effects and no hot spots) might even get a little bit wider.” Furthermore, the company does not think implant will go away; instead, it is believed the industry will end up using a combination of epi plus implant. “Even if you deposit an epi film, our customers are telling us that, to get maximum activation, LSA is beneficial.”

Figure 2. Planar transistor at 20nm showing LSA applications for front end and middle-of-line: a) traditional junction activation applications for which LSA has been used in previous nodes, and b) new applications that are expected to utilize LSA for the 20nm node. Applications are expected to be similar in regards to LSA for 3D structures at 14nm. SOURCE: Ultratech

Last thoughts

Paul Kirsch, director of front end processes at SEMATECH, told SEMI that he believes that each company will decide for itself what makes sense for its product set – either nonplanar architecture or ultra-thin SOI – to control short channel effects and leakage. “Intel is using tri-gate, but there are a lot of other papers published at conferences and journals that show other approaches,” said Kirsch. In the long run, however, he noted that the industry usually coalesces around one approach because that makes sense from infrastructure and cost standpoints.

Acknowledgements

VIISta is a registered trademark of Applied Materials.

by Debra Vogler, Instant Insight Inc., Sunnyvale, CA

“Not only must technologies used in the electronics industry come in at the appropriate cost points, but new ways of thinking about equipment design will be needed to support the level of innovation required to do so.” That is the basic premise of the talk by Sreenivasan Koduri, TI Fellow, to be presented in his paper entitled “Packaging Manufacturing Cost: Understand It Before You Can Reign Over It,” at the TechXPOT North at SEMICON West (Tuesday, July 10, “Contemporary packaging: achieving cost advantage through innovation”).

Factors contributing to cost include pure engineering and operations costs (equipment, people, materials, etc.) as well as the cost of manufacturing technology itself (equipment productivity) (Fig. 1).

Figure 1. Typical manufacturing cost contributors. SOURCE: Texas Instruments

With respect to equipment, Koduri calls for enabling parallel mass assembly. “One of the things bringing costs down is the number of units/strip,” said Koduri. Typically, a lead frame or strip used to have about 40 to 100 or 150 units/strip. “Now, that number is dramatically changing. There are some parts that are getting close to 10,000 units/strip.” Though he could not go into specifics at this time, Koduri said that Texas Instruments is working closely with its equipment partners to implement a greater capability for parallel mass assembly. He called for an order of magnitude improvement in the scale of parallel assembly, saying “Hundreds and thousands of units should be moved simultaneously.”

Koduri also maintains that suppliers haven’t completely broken out of very traditional ways of building equipment. “Take wire bonding. We still bond one wire at a time,” said Koduri. He also pointed out that it might be time to break out of the mindset of making one type of equipment fit all applications. “Maybe there are different types of equipment needed for smaller packages vs. larger packages, or high complexity packages vs. simpler packages.”

Providing an equipment supplier’s perspective, Manish Ranjan, VP of advanced packaging and nanotechnology at Ultratech, reported that the company is seeing an aggressive transition from wire bond design to flip-chip designs on the part of its customers. The move is being driven by performance requirements and form factor considerations. “We believe that at 28nm, 75+% of leading-edge logic designs will use flip-chip packaging, and at 22nm, virtually all of these devices could utilize flip-chip packaging,” said Ranjan.

Ultratech is also seeing a transition from eutectic bump/lead-free bump into copper pillar packaging. “We’re seeing the conversion right now at 28nm in Taiwan, in the wafer foundry and OSAT market segments,” noted Ranjan. “Moving forward, I have no doubt that copper pillar will become the dominant technology solution for packaging [of leading-edge logic devices].”

In the long term, Ultratech expects that through-silicon via (TSV) solutions will have the highest growth potential. “We believe TSV high-volume manufacturing (HVM) is a few years away,” said Ranjan. “There is a lot of work now being done on TSVs by memory companies, and we believe that the initial pilot production for these devices should occur within the next 12-18 months.” The outlook for logic, said Ranjan, is that use of TSVs will probably occur at the sub-14nm technology nodes for mixed device integration (logic and memory).

Until the industry is able to do TSV at high-volume for 3D ICs, however, the use of silicon interposers – or 2.5D solutions – will have to do. Lee Smith, founder and president of Lee. J. Smith Microelectronics Industry Experts observed that Xilinx has done a significant job of developing and promoting the 2.5D architecture. But getting even this intermediate TSV-based solution to be high-volume, high-yielding and cost-effective will pose significant supply chain issues. On the technical side, Smith pointed out that the new process technologies (a high-density of fine-pitch copper pillar micro-bump on one side, and C4 bumps on the other, and some 18,000 TSVs on a 150µm-thick passive silicon interposer) required to deliver a 2.5D architecture have yet to go through their cost/yield learning curve. On the business side, one has to consider that foundries have a market price they want to get for use of the required capacity – and that they are still seeing significant demand for 65nm, 300mm services. But interposers are large, and there’s a low number of good die per wafer, so the key, said Smith, will be whether the added performance advantages outweigh the cost in the early period of the 2.5D technology deployment.

Fabsurplus.com, a leading web-based remarketer of advanced equipment used to manufacture semiconductors and solar cells, today announced that Fabsurplus.com has been selected by Infineon Technologies as a remarketing partner for their surplus wafer fabrication, assembly and test equipment.

“Our customers worldwide are coming to recognise that Fabsurplus.com provides the best solution for online equipment remarketing, due to our multinational company structure, our technically competent sales team, our global market coverage and our innovative e-business software” said Stephen Howe, the Owner of
Fabsurplus.com.

“Our innovative approach and our dedication to providing a low cost sales solution both for equipment re-marketing and for the supply of used equipment has been rewarded by a marked increase in our business volume over the
last year, as well as the selection by our client Infineon of Fabsurplus.com as a valuable business partner.”

Customers can learn more about Fabsurplus.com’s remaketing and low cost sales solutions during SEMICON WEST 2012 by contacting the Sales Team ([email protected]) who will be attending the show.

Mark Bohr, Intelby Jeff Dorsch

Intel has resorted to “non-classical” scaling in making its 22-nanometer generation of chips, including the new third-generation Core “Ivy Bridge” processors, according to Mark Bohr, a senior fellow at the chipmaker and the company’s director of process and integration.

Giving the keynote address at Monday’s SEMI Gartner Market Symposium, titled “Silicon Technology Leadership for the Mobility Era,” Bohr summarized how Intel has done scaling of IC dimensions over the past two decades. “The ‘golden era’ of traditional or classical scaling served well for a long time,” he said. “But we were paying a price – leakage current,” Bohr added.

Classical scaling came to an end more than a decade ago with Intel turning to strained silicon technology for its 90-nanometer generation of devices in 2003, he noted. At the 45-nanometer node, and continuing with the 32-nanometer generation, the company resorted to another “non-classical” scaling technology, with high-K metal gates.

With the 22-nanometer generation, Intel has moved beyond planar transistors to tri-gate/finFET three-dimensional transistors, Bohr said.

“Intel is no longer a ‘one size fits all’ company,” he noted. “Now we are supporting a wider range of products.  We know how to make a high-performance, low-power chip.” 

That chip in particular is the “Medfield” Atom processor, which has 423 million transistors. The chip is made with Intel’s 32-nanometer P1269 system-on-a-chip process, according to Bohr. In the 32-nanometer generation, Intel developed both CPU and SoC versions of the process, and that differentiation has continued into the 22-nanometer generation, with the P1270 (CPU) and P1271 (SoC) versions.

The “Ivy Bridge” processor and other 22-nanometer chips are “a fully depleted device,” where the gate electrode has “more complete control,” he said. These chips have a lower voltage than devices based on planar transistors, with a 50 percent reduction in active power, Bohr added.

Oh, and “Ivy Bridge” has 1.4 billion transistors.

Intel currently has three wafer fabrication plants producing 22-nanometer chips, with another two coming on line by the end of the year, according to Bohr.

While 22-nanometer chips are in volume production today, Intel is currently developing 14-nanometer devices, and its research group in Oregon is “exploring a wide range of devices,” Bohr said. “Not everything they work on will pan out.”

He noted that Intel first published a paper on tri-gate technology in 2002, and it took another nine years before the technology was being used in volume manufacturing.

Competition from Asia, Unavailable Capital for Funding Affecting US Market

by Jeff Dorsch

When SEMI decided to give the 3rd Annual SEMI North American PV Fab Managers Forum the title, “Sustaining Business in a Changing Environment,” they were uncannily accurate about the “changing” aspect. The photovoltaic industry is now in something of a trough, with module and wafer pricing significantly down in the last two years as solar cell manufacturing has largely shifted to China and other Asian countries.

Despite the gloom and doom, several speakers at Monday’s event managed to accentuate the positive. “Solar is here to stay,” said Nasreen Chopra, vice president of capital equipment at Alta Devices. “We still have a lot of pillars here in the U.S.” She did acknowledge that pre-IPO companies in the photovoltaic industry currently face “a valley of death,” she added, with few opportunities to go public in the near future.

Still, there are 100,000 American jobs associated with the solar industry, noted Chopra, who also serves as co-chair of the SEMI PV North America Advisory Committee.

Other speakers at the event decried the election year politicization of photovoltaics as Republican politicians take shots at the recent failure of Solyndra. Joe Berwind, managing partner of AEI Consulting, said Solyndra has become “… a political football, baseball and basketball.”

With the stock prices of publicly held solar companies down, “solar will be at a disadvantage in raising money for the next two years,” Berwind predicted.

Shez Bandukwala of KPMG Corporate Finance said solar stocks are down 40 percent to 50 percent since April 2011, and the market is suffering from investor fatigue. When it comes to privately held companies, “there is no investor appetite for funding these companies” unless they have previously raised money, he added.

At the SEMICON West 2012 exhibition being held this week inSan Francisco, SEMI announced that it projects semiconductor equipment sales will reach $42.4 billion in 2012. According to the mid-year edition of the SEMI Capital Equipment Forecast released today, following a 9 percent market increase in 2011, the equipment market will contract by 2.6 percent in 2012. The year 2012 is likely to be the fourth highest semiconductor capital equipment spending year in history, with higher spending only in 2011 ($43.5 billion), 2007 ($42.8 billion) and 2000 ($47.7 billion). With $33.0 billion for 2012 forecasted for Wafer Processing equipment, it will be the second highest spending year ever for this segment, surpassed only by the $34.3 billion spent in 2011.

Denny McGuirk, president and CEO, SEMI “We expect 2012 to post one of the highest rates of global investment for semiconductor manufacturing equipment. Following a multi-year market expansion, sales will again exceed $42 billion — just one billion short of last year’s spending rate as the industry absorbs new capacity,” said Denny McGuirk, president and CEO of SEMI. “We also forecast accelerated spending to exceed $46 billion in 2013.” 

The drivers for this capital investment are consumer demand for tablet, smartphone, and mobile devices, leading chipmakers to continue to purchase manufacturing equipment to keep up with current production opportunities and to be ready to build chips based on new technology in the near-term future.  

For more information, see http://www.semi.org/en/MarketInfo

By Debra Vogler, Instant Insight Inc., and MySemiconDaily.com

At this year’s SEMICON West, you have an opportunity to participate in a manner that is different from past events. Whether you will be attending in person, catching the news online, or following the event from your office thousands of miles away, you will be able to connect with conference exhibitors and attendees by way of MySemiconDaily.com. If you attend an interesting new product demo and tweet about it – we’ll follow the conversation. Or perhaps you’ll tweet about a surprising bit of technology news – we’ll pick up on that as well. After the show, we’ll post a graph showing the hot products and discussion topics that captured the imaginations of show-goers.

To facilitate the process, I will be tweeting before, during and after the show – providing news updates, interesting quotes from industry executives, reporting from the various venues and receptions, and highlighting feature articles from the Show Dailies.

Please join me and the team at MySemiconDaily.com as we roll out a new way to participate in SEMICON West. It’s an opportunity to be more than a spectator at this exciting annual industry event. Follow Twitter handle @mysemicondaily; you can also follow my tweets by searching for #DebraVogler.