Intel expert talks about the drivers of future chip design and manufacturing
Mark Bohr, senior fellow and director of Intel’s process architecture and integration, sat down with SEMICON Daily News to talk about the company’s push into Tri-Gate, its future SoC direction and drivers for chip design and manufacturing in the future. What follows are excerpts of that conversation.
SDN: Will Tri-Gate be as repeatable for other types of less regular SoCs as for Intel’s processors?
Bohr: Yes. All of this is base technology that is intended to meet the needs of a wide range of products. That’s certainly true for the 22nm generation. The same Tri-Gate structures will be used on our high-performance processors as well as our low-power and SoC types of products.
SDN: Intel has always tried to limit the number of masks it uses for economic reasons. Can others do that, and can Intel do that for other types of chips?
Bohr: Intel historically has tried to minimize costs with the number of masking steps. That’s our goal on any technology — to deliver the best-possible density and the best-possible performance at the minimum amount of mask-out. But that’s getting more difficult for all of us. At 22nm we have to either start adding more interconnect layers to meet the needs of the high-performance processors or we have to start using more double-patterning layers to get down to the tight pitches and tight design rules. We’re still very cognizant of and sensitive to keeping wafer costs low, but our processors — which range from high-performance to low-power Atom SoCs — will not use the same number of interconnect layers.
SDN: Is Intel looking at 2.5D and 3D stacking?
Bohr: Yes, absolutely. It’s not only how to optimize the transistor on the chip, but how you package multiple chips into a 3D form factor. We’ve been exploring TSV technology and 3D packaging for quite a while, and they’re coming along.
SDN: Is Wide I/O a major factor in this?
Bohr: That’s one of the ways to use 2.5D and 3D stacking. You can have a Wide I/O memory chip, which has better memory bandwidth at lower power so the memory solution is more power efficient. But these small handheld devices also are very cost sensitive. What’s holding us back now are the cost issues around TSVs and 3D stacking. We see that solution coming, but it will not be widely adopted very soon.
SDN: Is it a matter of volume and experience?
Bohr: It’s that and drilling through the wafer and thinning down the wafer for stacking. Those are expensive added steps.
SDN: Is this all still bulk CMOS forever?
Bohr: When we looked at our Tri-Gate technology, we settled on a bulk wafer. You can also make Tri-Gate or FinFET devices using SOI wafers, and some people may choose that. We felt our bulk approach was a bit more cost-effective, but there’s a good chance over the next five years that other companies will produce FinFETs using SOI wafers.
SDN: How about new channel materials? There was talk about indium gallium arsenide in the NFET and germanium in the PFET.
Bohr: Intel has been pretty active in researching that and publishing papers. Every year we’ve presented data at IEDM on channel materials. This is another good example of how we’re trying to explore new materials and new device structures to reduce operating voltage. Three to five channel materials may get us from 0.7 volts down to 0.5 volts.
SDN: Where do we stand with EUV and eBeam?
Bohr: It probably won’t be available at 14nm, but we’re hoping it will be available for the generation after that.
SDN: What does that buy you?
Bohr: What Intel always does for technology as important as lithography is to pursue multiple parallel paths. When it comes time, that way we have more than one choice. We choose the one that best meets the dimensional capabilities as well as the cost. We have had our hopes on EUV for some time, but luckily we’ve also pursued immersion and double patterning in parallel. That has come up better than most of us dreamed possible. It’s not that EUV isn’t there yet, but double patterning with immersion has really delivered.
SDN: So you can get by with double patterning and immersion for the foreseeable future?
Bohr: Yes.
SDN: What will finally force a shift, if anything?
Bohr: It will come down to cost. Are two immersion-patterning steps more cost effective than a single EUV step? Right now, double patterning is more cost-effective.
SDN: When you look out a couple nodes, what does a chip look like? Is it still planar and denser, or is it a completely different approach?
Bohr: One important perspective is that chip technology is becoming more heterogeneous. If you go back 10 or 20 years ago, it was homogenous. There was a CMOS transistor; it was the same materials for NMOS and PMOS, maybe different dopant atoms. That basic CMOS transistor fit the needs of both memory and logic. Going forward, we’ll see chips and 3D packages that combine more heterogeneous elements, different materials, and maybe transistors with very different structures, whether they’re for logic or memory or analog. Combining these very different devices onto one chip or into a 3D stack — that’s what we’ll see. It will be heterogeneous integration.
SDN: It sounds as if you’re venturing heavily into the SoC world, where Intel hasn’t really been a force.
Bohr: Mainstream microprocessors are very much like an SoC chip. They’re not quite like what you expect in a smart phone, but if you look at the Sandy Bridge chip compared with a processor 10 years ago that was just logic transistors and SRAM memory. Today’s chips have integrated logic controllers, integrated graphics, a lot of analog elements and phase-lock loops. If you go into a different market, like a true SoC chip for a smart phone, then you have even more integrated functions. But that’s where Intel and our industry are headed — integrating more functionality into a small form factor, whether it’s an SoC or a 3D stack.
SDN: Is part of the goal to sell the whole device, or maybe just a piece of the device?
Bohr: The technology goal is to integrate as many functions into the smallest possible form factor for the lowest possible power. From a business perspective, a company that can do as much of that combined stack as possible will be in a better place than if you’re just one of the component suppliers.
SDN: But you probably won’t develop all the pieces yourself, right? For that, you’re going to need partners.
Bohr: Yes, and that’s the expected tension. Do you do all the pieces and control the full integration or do you do better if you pick and choose pieces from partners in the industry? The winning solution will probably be a compromise of those two. You may not do everything on your own, but maybe you do most of it.
SDN: This is a massively broader market for Intel.
Bohr: Intel is re-inventing itself. We are getting much more into this SoC business, and it requires different skills and interests as we put together all these pieces.
SDN: As a large IDM, Intel has the ability to define what goes where on a chip and how the chips that are stacked with it are designed.
Bohr: I don’t disagree with that. The more technology pieces you control internally, so you can do that co-optimization, the better the technology will be and the better your business will be.
SDN: Does that mean you now push only certain pieces to the bleeding edge of Moore’s Law?
Bohr: That’s certainly one of the options, and one of the desirable features, of the 3D stacking approach. You don’t have to use leading-edge technology to do the whole chip. You can use the right technology for the right part of the system.
SDN: And quickly, too, right?
Bohr: Yes.
SDN: Most SoC developers are talking about more software content. Will that be part of this focus, particularly with the Wind River acquisition?
Bohr: I’m not a software expert, but one thing that is not well known is just how large of a software company Intel is. Wind River was just one acquisition, but we are one of the top companies in the world working on software.
SDN: But are the software and hardware teams now working together?
Bohr: There is a lot of collaboration. It’s not enough just to offer a certain core. The SoC circuits have to be optimized for the software.
– Ed Sperling
CEA-Leti, the applied research center for microelectronics and for information and healthcare technologies located at the MINATEC consortium in Grenoble, France, has announced that the IMAGINE Maskless Lithography Workshop will be held September 6, 2011 at the Keio Plaza Hotel in Tokyo, Japan.
The Workshop agenda includes a technical update on the program’s main achievements, updates on MAPPER’s technology roadmap, and discussions on lithography options for the 22nm and future manufacturing nodes. 
Photo: Info-EconomiqueSpeaking at SEMICON West in July 2011, Leti CEO Laurent Malier noted the significant progress made at Leti during the last year. “Leti’s focus on semiconductor technologies, including design, chemistry, and characterization,” said Malier, “will have impacts on applications in many parts of the global economy.” The core Leti research work is on semiconductor manufacturing technologies, noted Malier, but the application of these leading-edge technologies will advance health care, energy management, and many other fields. Click here to view M. Malier’s SEMICON West presentation.
