450mm Wafer Manufacturing Tools Ready

The long-debated transition to semiconductor processing using 450mm diameter silicon wafers — the next size after 300mm — has reached a major milestone with new tools released for the production of bulk silicon and silicon-on-insulator (SOI) wafers. Before original equipment manufacturers (OEM) can begin developing IC fabrication tools, the wafer manufacturers need the capabilities to produce the substrates needed for process development and integration. During SEMICON West 2011, KLA-Tencor announced the availability of a 450mm unpatterned wafer inspection system, and EV Group unveiled the first bonding system for 450mm SOI substrates.

KLA-Tencor’s next generation of wafer defect and surface quality inspection systems, the Surfscan SP3, is designed for extension to 450mm (figure). As the first unpatterned wafer inspection platform to incorporate deep-ultraviolet (DUV) illumination, the tool feature dramatic advances in sensitivity and throughput over the prior SP2XP model. The SP3 also offers a module that inspects the back side of wafers for defects that might deform the wafer shape during photolithography.

The Surfscan SP3 system is designed to help develop and manufacture substrates for <28nm devices that are nearly atomically smooth and free from polish marks, crystalline pits, terracing, voids or other defects that disrupt the electrical integrity of the transistor. Because these defects cannot be reliably detected by current-generation inspection systems at production speeds, substrate manufacturers have had difficulty achieving satisfactory yields with these top-grade, next-node wafers. KLA-Tencor’s engineers have built the Surfscan SP3 inspection system with the DUV sensitivity and throughput needed to reliably identify critical defects and surface quality issues inline during substrate manufacturing.

EV Group unveiled the semiconductor industry’s first bonding system for 450mm wafers manufactured from SOI substrates this week. Building on EVG’s strength in SOI wafer bonding, the new system — dubbed the EVG850SOI/450 mm — was created to support and facilitate the industry transition to 450mm wafers from the current 300mm standard. Leading SOI wafer provider Soitec will install, test and qualify the first of this new system at its Grenoble, France, headquarters, starting in the fall of this year.

Noted chief operating officer Paul Boudre of Soitec, “With the launch of this new system, EV Group is offering the semiconductor industry a highly viable solution to ease the transition to 450mm wafers. With our well established SOI material playing an increasingly greater role in fabricating next-generation ICs, we look forward to working with EVG to ensure this new system is ready to enter mainstream production in a timely fashion.

Because chipmakers will need an interim solution to optimize productivity for existing 300mm capacity as the migration to 450mm proceeds over the next few years, the system can serve as a bridge tool, allowing processing of both wafer sizes.

“Every bonded 300mm SOI wafer and nearly 100 percent of all SOI wafers are fabricated on EVG systems. We delivered our first SOI bonding system in 1994, and our global installed base continues to grow with widened adoption of SOI substrates,” noted EV Group executive technology director Paul Lindner.

BrightSpots 450mm online forum

Lindner was one of the panelists who launched an online 450mm web forum in a live panel discussion July 11 in San Francisco. Other panelists at the “BrightSpots” live event, sponsored by public relations firm MCA, were Michel Brillouet, executive with CEA-Leti; Risto Puhakka, president of VLSI Research; and Gus Richard, analyst with Piper Jaffray.

Much of the concern regarding the transition to 450mm wafers is due to the OEMs’ painful experiences in transitioning from 200mm wafer to 300mm wafers. There was excessive promotion of the global need for 300mm wafers ahead of the real demand so that OEMs invested resources into bringing tools to market only to be told that the market wasn’t ready yet. In some cases, the tool was designed for the specifications of a particular technology node and then had to be redesigned to meet the specifications of the next node when the real demand started.

Puhakka reminded everyone of one of the key lessons from the last wafer size transition: the economics completely change before and after the transition. Before the transition, 200mm wafer tools were the proven conservative approach to production. After the transition to 300mm, 200mm lines could not compete on a cost basis and some companies were stuck with uncompetitive billion-dollar investments. So, presuming that an IC manufacturer anticipates running sufficient volumes of chips to be able to justify the capacity of a 450mm fab, it should be far less expensive than running two 300mm fabs. “No company wants to be the last to build a 300mm fab,” reminded Puhakka.

Who can afford a 450mm fab? Richard quipped that it’s “ITS: Intel, TSMC. And Samsung. The issue is the factory is going to cost $9 to $12 billion dollars, so the revenue run-rate will have to be $15 to $20 billion.

When will the first 450mm IC fab come on line? “Volume manufacturing at 450mm is probably about five years away, but development has to start now,” said Lindner. “I think that every major tool maker has a 450mm program even though they might not talk about it in public. So the tool development is underway, but the hurdle today is the process development and integration.”

“Even for 14nm it is probably too late, so the first possible insertion node will probably be 10nm or below,” said Brillouet. Puhakka responded that he’s not sure about the specific node, but VLSI Research has been saying for many years that the time frame for 450mm will be 2020 to 2025.

The BrightSpots 450mm discussion continues asynchronously online through the end of next week. Join in the conversion, and post questions to these experts at www.infoneedle.com/MCA450 until July 22.

– Ed Korczynski

Likely Implementations of Printed Electronics Will Require Mobile Power 

Printed devices have been around for a long time. A few transistors here, optoelectronic and photovoltaic elements there, maybe an RFID tag or a ring oscillator. But commercial products are built around complete systems, not individual devices. As Ana Claudia Arias of UC Berkeley pointed out at the Materials Research Society Spring Meeting in April, complete systems incorporate several different elements. For example, a device to track a soldier’s exposure to concussions might need a pressure sensor or accelerometer, but would probably also include an amplifier, a detector, a clock or other time stamp capability, and memory. Additional circuit elements would be needed to facilitate data retrieval, whether through wireless transmission or some other means. All of those functions need power.

Current generation small electronics depend on coin batteries, but even those are often too big and too expensive for printed electronics applications. Consider the thickness that a battery would add to a smartcard, or the cost that a battery would add to a disposable sensor or smart bandage.

So where does the power come from?

Photovoltaics offer one possible answer. At this week’s Extreme Electronics session on printed and flexible electronics, to be held Thursday at the Extreme Electronics TechXPOT in South Hall, Vishal Shrotriya, technology director of Solarmer Energy, will review recent developments in cell architectures and manufacturing processes for organic photovoltaics (OPV). His presentation discusses work on improved efficiency and device lifetime: though OPV can now achieve conversion efficiencies in the neighborhood of 9%, they still fall short of the benchmarks set by inorganic PV. Shrotriya’s talk also outlines the development of roll-to-roll production processes, which are essential both for low-cost production of OPV and for integration of photovoltaics with other printed circuit elements.

In the same session, NanoMarkets principal analyst Lawrence Gasman will discuss his firm’s recent analysis of the printed battery and printed photovoltaic sectors, as well as other printed and flexible electronics markets.

Although Arias views printed batteries as an enabling technology for printed electronics systems, it is not yet clear where the best market opportunities lie, given the current state of both printed electronics and printed battery technology. While applications like flexible, printed displays are often discussed, real world applications are so far much more prosaic. For example, Power Paper has designed a cosmetic patch that uses printed batteries to drive moisturizers and other active ingredients into the skin. The same technology could also be used for medical patches, and it is easy to imagine the gradual incorporation of more sophisticated electronics, turning a simple drug delivery patch into a smart bandage that monitors and assists wound healing.

Printed electronics are also being considered for use in sensor nets, such as a vibration or stress-sensitive net that wraps around an airplane wing, or an array of wireless proximity sensors used to monitor traffic through an area. Proximity and other environmental sensors are a particularly interesting case. The individual sensors can build their own network, with each sensor reporting its data to its neighbors until a bridge is formed to a central data storage and transmission point. This approach allows many sensors to fail — whether through device failures or destructive environments — without compromising the network as a whole.

The underlying premise of such a sensor network is that the individual devices are simple and inexpensive enough for the user to distribute hundreds or thousands of them. This requirement makes roll-to-roll printed electronics a natural fit. Some sensors might use printed batteries, but others might turn to energy harvesting devices: a piezoelectric sensor that flexes under stress might also generate the power it needs to broadcast or store its data.

The printed and flexible electronics worlds merge in more closely coupled networks, such as stress-monitoring nets or an array of sensors built into clothing for hazardous environments. In these examples, the sensors are connected to each other and to a central controller by wires, but the network of wires needs to be flexible enough to conform to a surface. Another speaker in the Extreme Electronics session, Stan Farnsworth, VP of marketing at NovaCentrix, will discuss printing of copper oxide on paper using conventional screen printing methods and the subsequent reduction of the lines to copper thin film.

– Katherine Derbyshire

New York Fab to Start Load-In 

Marking the transition from a construction phase to operation phase, Globalfoundries has said its new 300mm fab build-out is ready for equipment (RFE). The Globalfoundries’ newest facility is Fab 8, located at the Luther Forest Technology Campus in Saratoga County, New York. Fab 8 will focus on leading-edge manufacturing at 28nm and below. In addition, at Fab 1 in Dresden, Germany, the foundry has completed construction of an additional wafer manufacturing facility designed to add capacity at 45nm and below.

For more information, visit www.globalfoundries.com

New Fab Equipment Ready

Marking the transition from a construction phase to operation phase, Globalfoundries has said its new 300mm fab build-out is ready for equipment (RFE). The Globalfoundries’ newest facility is Fab 8, located at the Luther Forest Technology Campus in Saratoga County, New York. Fab 8 will focus on leading-edge manufacturing at 28nm and below. In addition, at Fab 1 in Dresden, Germany, the foundry has completed construction of an additional wafer manufacturing facility designed to add capacity at 45nm and below.

For more information, visit www.globalfoundries.com

CEA-Leti Announces Improvements 

MEMS-based technology continues to be highlighted at this year’s SEMICON West show. Today, CEA-Leti announced that its RF MEMS switch technology has been significantly improved. The new switch design is based on a dielectric-less solution in which an air gap is used to prevent switch contact. Small dielectric dots placed under the mobile electrode provide the necessary air gap. Long-term tests show a drastic improvement in reliability with no pull-down voltage drift. The new switch-manufacturing process has been demonstrated on 200mm silicon wafers on the MINATEC-dedicated MEMS fabrication platform. 

For more information, visit www.leti.fr

Backside Heating Maintains Even Temperatures Across Wafer 

Applied Materials launched its Vantage Vulcan rapid thermal processing (RTP) system, employing wafer backside heating to improve the temperature uniformity across individual die.

Sundar Ramamurthy, general manager of Applied’s Front End Products Group, said die sizes have grown larger in recent years, making it more challenging to control the annealing temperature across the dense and less-dense areas of the die. That led Applied to develop a backside heating RTP system, a first for the industry, which resolves pattern-loading effects.

Compared with direct radiant heating, the backside heating approach reduces the hot spots across the patterned wafer, reducing the transistor performance variations, which often result in more poor-performing chips on the wafer, he said.

The honeycomb-like array of lamps is configured into 18 zones, controlling a much wider range of temperatures — from 75°C to 1,300°C — compared with Applied’s earlier RTP systems. By using backside heating, the temperature variability was reduced from 9°C to <3°C, even while the wafer temperature is aggressively ramping at more than 200°C/second, to a maximum of 1,300°C.

Channel depth is an important issue, particularly as leading-edge companies go to fully depleted architectures with thin vertical or planar channels. RTP heats the silicon channel’s top atomic layers, activating dopants and transforming the silicon from an insulator to a semiconductor. Differences of just a few degrees Celsius can change the channel depth enough to make a major difference in leading-edge ICs.

Ramamurthy said contact materials also are coming in that require lower temperatures. “This ability to operate at less than 250°C is huge for our customers” as they seek to reduce contact resistance, he said. RTP converts a contact silicide material, such as nickel platinum, to a more robust nickel mono silicide, improving the contact resistance.

Shankar Muthukrishnan, the global products manager for Applied’s RTP products, said “Vulcan turns RTP upside down.” The lamp array is positioned underneath the wafer’s backside, where the pattern is uniform, eliminating the variability that comes from front-side heating.

“We can match every feature to within 3°C, even when we are heating up the wafer at a rate of 200°C, up to the maximum temperature of 1,300°C.

The Vantage Vulcan includes closed-loop control, which dynamically controls the wafer temperature as the tool ramps from near room temperature to 1,300°C. The capability enables any device wafer, including wafers with challenging reflective surfaces, to be processed without recipe modifications — a benefit for the high-mix, fast-changing environment of foundries, Ramamurthy said.

Applied has been working with early customers, and the company has received repeat orders from customers beginning to ramp their 28nm technology to volumes, he said. He estimated the RTP-served available market at $500 million.

– David Lammers

Companies Will Collaborate on Process Technologies

Intermolecular Inc. announced on July 11 that it will collaborate with Globalfoundries on research and development of a wide range of semiconductor process technologies. Under a newly signed multiyear collaborative development program (CDP) and intellectual property (IP) licensing agreement, Globalfoundries will use Intermolecular’s high productivity combinatorial (HPC) technology to accelerate the creation of process modules that will be integrated into manufacturing lines worldwide. Much of the development work will be performed at Intermolecular’s HPC R&D Center in San Jose, CA, in close collaboration with the foundry’s operations in Germany, New York, California, and Singapore.

“We’re especially pleased to work with Intermolecular to accelerate development not just for our most advanced technology nodes, but also for mature production lines, where we provide a wide variety of scalable plug-in modules to help our customers meet the widest possible range of market opportunities.” said Gregg Bartlett, Globalfoundries’ senior vice president of technology and research and development.

Intermolecular’s HPC technology enables generation and analysis of experimental data with significantly greater speed and efficiency than a traditional development line. Researchers and engineers from both companies will work side by side, using Intermolecular’s full suite of Tempus wet-workflow development systems and Tempus AP-30 platforms, which can perform ALD, CVD and PVD deposition processes. Intermolecular’s Informatics software allows rapid analysis of the resulting data, and quick identification of the most promising results.

“We’re very excited to be working with Globalfoundries” said David Lazovsky, Intermolecular president and CEO. “This is an extensive and diverse engagement, covering technology nodes from 45 nm down to 14 nm, spanning multiple process and device integration applications.”

–Ed Korczynski

Future 3D Chips May Need 1D Litho

Lithography alone always used to define the smallest lines on ICs, but affordable patterning for 22nm node and beyond will require contributions from engineers working in not only lithography but also design, etch and deposition. The Advanced Lithography session Wednesday morning from 10:30am to 12:30pm in the NorthOne TechXPOT in Moscone Center will feature the latest updates to the EUV lithography infrastructure, ways to push optical lithography past the normal resolution limits, and ways to complement optical lithography with E-beam direct write (EbDW) technologies for future nodes.

The EUV lithography infrastructure of steppers, 13.5nm wavelength sources, and resists continues to improve, but it seems to have missed the insertion time for 22/20nn node manufacturing. Thus, 193nm wavelength immersed in water (193i) steppers will have to be used for the next node again. The Metal-1 pitch for the 22/20nm node will be ~64nm, which is well below the 80nm limit for single exposure. Double-patterning (DP) using various approaches will have to be used, which creates new challenges for EDA, and mask-makers will have to manage layer fractioning.

At IEDM 2010, Samsung researchers showed sidewall spacer double-patterning (SSDP) will be used for 2Xnm half-pitch Flash chips, but in a variation Samsung terms “self-aligned reverse patterning” (SARP), where the sidewalls define the pattern instead of the cores/spaces. The CD uniformity of SARP is reportedly <5%, compared to >10% when trying to use the cores/spaces of self-aligned double-patterning (SADP), and the improved uniformity reduces threshold voltage (Vth) distribution.

After Double Patterning a Single Dimension

The only way to regain manufacturing margin in lithography is to sacrifice a degree of freedom in design and restrict all patterns in a mask to arrays of parallel line segments, just as Intel has been doing for the last few nodes. In so doing, dipolar and other off-axis illumination can be combined with phase-shifting masks to squeeze the 193nm light into the smallest possible grating patterns.

Pushing the limits of 1D design is possible with double-patterning (DP) when gridded design rules (GDR) are used to make uniform arrays, followed by pitch-splitting, a.k.a. frequency multiplying, to get to sub-wavelength resolution features and a final “cut” pattern of selectively placed orthogonal line segments (figure). The cut layer thus becomes the most critical in terms of lithographic parameters, with similarities to the hole patterns used in contact layers.

At the SPIE Advanced Lithography conference held earlier this year in San Jose, Valery Axelrad of Sequoia Design Systems and Michael Smayling of Tela Innovations presented results from collaborations with Canon on “Optical lithography applied to 20nm CMOS logic and SRAM.”

Optimization variables for the cut layer include the cut geometry (width, height, serifs), illumination of the scanner lens entrance pupil, and grouping cuts in similar optical environments to allow for local OPC. The optimization was for the CD error across all cuts, which also reduces variation among cuts by getting all CDs close to the same target value. This reduction of variation substantially simplifies the layout and OPC and produces manufacturable designs, including both SRAM and logic.

There are many ways to formalize GDR+cut DP litho, but Tela and partners propose the following 1D rules:

• Highly uniform 1D GDR layouts with sparse identical cuts,
• Critical layers are cuts,
• All cuts identical to each other and tripled to ensure yield,
• Cuts also on a fixed grid (avoiding difficult neighborhoods),
• Interactions between cuts sufficiently small for local iterative OPC to converge using SMO, and
• Use of a M0 layer to reduce the number of cuts and improve uniformity of cut density.

An algorithm was developed to resolve OPC and SMO for critical cut and hole layers:

STEP1: SMO (a.k.a. “co-optimization”) to find optimal cut shape and size, and illumination of the scanner lens entrance pupil (source) using a small representative sample portion of the layout.

STEP2: Local layout correction (pseudo-OPC) using information from Step1 to create the ideal size for the rectangles at each location: some a little smaller and some a little larger. Typically only 3 to 5 iterations are needed to reach <1 nm RMS CD for a 42nm target CD, which takes 30 to 60 seconds on a quad-core CPU, for a total simulation time of ~2 hours on a single CPU for ~120 windows.

The test chip was a 100k MOSFET, including 50 different standard cells for SRAM and logic, in 50 x 60 microns area, using a 3 x 3 microns SMO sample window. The optimal illumination was a horizontal dipole.

Complementary e-beam Lithography 

Dr. David Lam, founder of Lam Research Corporation and currently chairman and CEO of Multibeam, will provide an overview of EbDW integration strategies in the TechXPOT Wednesday. EbDW can be used to “cut” the lines formed by SSDP 193i steppers so as to get the best combination of resolution and lithography-module throughput. EbDW can also be used for contact layers, perhaps using shaped apertures to make trenches instead of holes. When used to complement optical lithography, Lam calls EbDW complementary e-Beam lithography (CEBL).

Lam will discuss how CEBL plays a balancing and crucial role in meeting the industry’s patterning needs at advanced nodes, and also extends the use of current optical lithography technology, tools and infrastructure. The CEBL infrastructure exists for pitch-division tools, EbDW equipmentunder development, e-beam resists, e-beam wafer inspection, EDA tools and yield management software. This ecosystem offers a cost-effective, complete solution that scales far beyond 20nm nodes.

-Ed Korczynski

TSV Interposers and True 3D ICs using TSV

Through-silicon vias (TSV) have been in R&D for more than 10 years and are finally scheduled to reach commercial use in IC manufacturing this year. Vias will be made through silicon both in active ICs (3D-IC) and though silicon interposers (2.5D) made in outsourced test assembly and packaging (OTAP) fabs.

Many workshops and TechXPOTS at SEMICON West this year will deal with the real-world issues of commercial manufacturing of TSV, including supply-chain business models and the need for new EDA models. On Wednesday morning, July 13, from 9:00am to 12:00pm in the San Francisco Marriott Marquis hotel, SEMI/SEMATECH will hold a workshop on “3D Interconnect Challenges and Need for Standards.”

Different original equipment manufacturers (OEM), specialty materials suppliers (SMS), and consortia have created TSV along parallel private roadmaps. In addition, there are “boutique” companies providing custom 3D-IC advanced-packaging services for military and aerospace applications looking to expand into high-volume commercial markets. The result is a confusion of options, and no real cost or yield data for volume manufacturing. Nonetheless, after more than 10 years of R&D and pilot work, TSV are finally scheduled to be produced this year in limited commercial volume.

After considering the many options to form TSV through active silicon, the world has settled on two: 

1. Via-Middle, TSV after transistors and tungsten but before multi-level Cu interconnect, with 3 to 5 micron diameter and 50 micron deep vias etched “blind” into full thickness wafers in the fab, and
2. Via-Last, TSV etched to a stop layer from the backside of thinned wafers temporarily bonded to carriers at an OTAP, with 8 to 10 micron diameter and 50 to 100 micron deep vias.

The via-middle TSV etch being “blind” means that it never sees a stop layer and just etches for a certain time, creating a greater challenge for controlling uniformity in etch chambers.

For interposers made using silicon wafers, the final target thickness will be 100 to 140 microns. Interposer thickness cannot be reduced below 100 microns without rigid silicon wafers becoming flexible silicon foils that generally cannot be handled by automated robotics. Typical TSV processes to date have worked with 5 to 10 micron diameter vias, which results in the need for integrated process flows capable of etching and filling 10:1 to 20:1 aspect ratio (AR) structures. Silicon interposers (2.5D) have near-term applications including high performance network systems, laptops, tablets, mobile systems, and game consoles.

Georgia’s Institute of Technology (GT) has a Packaging Research Center (PRC) that has been working on TSV and 3D packaging under packaging guru Rao Tummala. At a SEMI-sponsored pre-show webinar, Prof. Tummala discussed some of the ways to reduce interposer costs using panels of poly-silicon instead of wafers of single-crystalline silicon. Starting with 200-micron thick poly-Si sheets, Tummala’s process uses lasers to drill vias and then a polymer deposition to form insulation instead of oxidation. Glass could be used as the interposer material with advantages for some applications (figure), so there are now many different applications for silicon or glass interposers (SiGI).

Will silicon interposers be a temporary stop or a solid fork in the highway for 3D progression? How will silicon interposers integrate with Cu pillars? How should the industry tackle memory stack assembly with TSV? Speakers including Prof. Tummala will discuss possible answers to these and related questions on Wednesday afternoon, 1:30pm to 5:00pm, in the Moscone NorthOne TechXPOT, when the SEMI Advanced Packaging Committee of the Americas will host “3D in the Deep Submicron Era.”

– Ed Korczynski