3D Stacking and Structures Call for More Atomic-Level Precision Manufacturing Steps

Omkaram (Om) Nalamasu, CTO of Applied Materials, sat down with SEMICON Show Daily to talk about what’s changing in semiconductors and how that will affect manufacturing equipment. What follows are excerpts of that conversation.

SSD: 3D stacking and 3D structures represent an inflection point for semiconductors. What does that mean for manufacturing equipment, though?

Nalamasu: The number of steps, as well as the complexity, will go up. We will need more materials to get energy-efficient performance. So there will be innovations at multiple levels. At the heart of all of this, and the ability to drive Moore’s Law forward, however, is the ability to control thin films with atomic precision. Innovations in equipment are fundamental to reach atomic-level engineering.

SSD: How do we deal with process variability?

Nalamasu: We continuously make improvements in this area. Chamber matching is one activity we’re pursuing—wafer to wafer, batch to batch. Repeatability needs to be improved.

SSD: Will it be CMOS forever? There were also predictions that CMOS would run out of steam by now.

Nalamasu: In the foreseeable future, it will be CMOS. Whether it is forever is difficult to answer.

SSD: Where are we today with TSV manufacturing?

Nalamasu: The TSV solution has progressed to the point where several players are doing pilot-line activity. Some issues need to be resolved, but I don’t think those are insurmountable. It’s a question of time, innovation and collaboration.

SSD: The other 3D involves structures. How does that affect equipment?

Nalamasu: 3D transistors are more complex, but complexity is our friend. It requires synthesis of new ideas from multiple disciplines of science and engineering. A lot of work has occurred in 3D transistors, but Intel has announced a major step. It is taking 3D transistors toward production, playing toward Applied Materials’ strength.

SSD: Is Intel unusual, though, because of the very regular structure of its chips?

Nalamasu: Intel certainly leads us in taking this technology to manufacturing, both in process and design, but there will be many more industry innovations as well.

SSD: Where do you see the next big bottlenecks?

Nalamasu: Low-power performance is critical for any of the mobile applications. To continue scaling down cost-effectively while addressing leakage is a fundamental issue for the industry to move forward. Connectivity is another inflection point.

SSD: What kind of connectivity?

Nalamasu: Connectivity at a broader level of multiple devices. How to do it in a seamless, secure, and cost-effective way.

SSD: So this is similar to the Internet of things?

Nalamasu: Absolutely. There are about 6 billion devices out there. There is a lot of opportunity for these devices to interact.

SSD: If you’re putting together multiple process technologies on a 3D stack, does that extend your opportunity?

Nalamasu: Heterogeneous integration has been the subject of intense interest for the past 15 years. A 3D TSV is the first step toward realizing that potential, but there is a lot more opportunity and white space as we move from integrating silicon to silicon to integrating silicon to MEMS and other devices.

SSD: Does that extend your world, though?

Nalamasu: There are a lot of opportunities in both extending Moore’s Law and in serving other markets such as solar and LED. We look at opportunities to sustain the scalability, but we also look at new markets and opportunities. We do quite a bit of R&D.

SSD: Moving up a level of abstraction, how does the manufacturing industry change over time?

Nalamasu: It’s already a global industry. Consolidation will continue as the cost of building a fab goes up. Presumably, there will be some consolidation in the equipment provider industry as well, as the cost of R&D goes up.

– Ed Sperling

Who Will Be Responsible When a Stacked Die Fails? So Far, The Answer Isn’t Clear

The shift to stacking die raises some interesting technology challenges — how to model through-silicon vias (TSV), how to deal with physical effects such as stress, heat, and noise, and how to deal with electrical issues such as electrostatic discharge. But the more immediate hurdle to jump-starting this market appears to be on the business side.

From a technology standpoint, a 2.5D stack initially can be built using the same formula and methodologies as PCBs, multi-chip modules and systems in package, which are hardly new concepts. In fact, they are well tested and have been widely deployed in the past. Building a 3D stack (figure) with TSVs will be tougher because it relies on new technology that has not been well tested and proven. But in both cases, there will be an additional challenge: turning this into a commercially viable model that allows massive re-use, particularly of analog from previous process generations, as well as merchant IP.

The IP in these stacked die may include everything from a subsystem to a full chip, and it may include internally developed die, subsystems, and blocks as well as commercially developed versions. That raises some interesting challenges, though, because what constitutes a good die in a planar configuration may not work as well — or sometimes not at all — in a stacked configuration.

The big question is: Who is responsible for that failure? Is it the maker of the subsystem or die? And if so, which one? Is it the maker of the die that doesn’t work in a particular stacked configuration or the maker of the die that caused the other die to fail? In some cases, two known good die may both fail when stacked together. And does the liability rest with the company putting those die together because its engineers should have characterized the physical effects of the die that were being stacked?

This becomes even murkier as design meets manufacturing. Die need to be thinner in stacked configurations, which means the physical effects are more pronounced. Noise from an I/O interface, for example, may have no effect at all on a single die, but it could disrupt a sensitive analog signal in a stacked arrangement. In addition, there are new technologies that need to be accounted for, most notably TSV, which don’t necessarily expand and contract at the same rate as silicon.

“At advanced nodes, the die is thin so the TSVs through the die can add to the complexity of stress,” said Amit Marathe, manager of reliability and modeling at GlobalFoundries. “Initially there will have to be restrictive design rules to make sure that stress does not interfere with device performance. You need sufficiently long distances between the devices on a chip.”

Getting this formula right is critical for the semiconductor industry’s continued progress, especially since multiple companies need to share information. That kind of information has been considered proprietary in the past, and inside of many companies it is still considered a competitive edge. Still, the business case for cooperation is high. In addition to NRE costs and missed market windows, stacked die also scale the bill of materials by as many times as there are layers.

“What 3D stacking adds is more ways of hurting or helping ourselves,” said Drew Wingard, chief technology officer at Sonics. “Once you winnow the choices based on economics, then you have to figure out what are the high-level user benefits. You may get more features, save power or energy, and optimize on cost. You can see that in Apple’s approach to SoCs. Some of their products have been done with components that are behind the competition, but their focus on the user is so strong that they always hit it right.”

3D also provides the opportunity to improve performance and energy efficiency by widening the channels and shortening the distance that signals need to travel. In fact, it was the possibility for enormous improvements in performance that first led to research on stacking of die at companies such as IBM in the early part of the millennium. At the time, being able to save power was considered a secondary concern. Since then, with a focus on more mobile devices, the priorities have been reversed, with re-use of analog and flexibility in what gets stacked on something else now a close second.

“This opportunity is massively wide and very appealing to a lot of customers,” said Simon Segars, executive vice president and general manager of ARM’s Physical IP Division. “But it also has a bearing on how you develop IP, which will have thousands of connectors up to memory. We have R&D work going on with IP, bandwidth issues, and the physics of how to put this all together.”

And there are standards organizations — most notably Si2 — that are working to develop standards for how the technology goes together. But to really get stacking going, one of the big challenges is less about the technology and more about the ability to share responsibility — and risk — to make the stacked die work as planned.

– Ed Sperling

A Perspective from ClassOne Equipment

In the past few years, companies like ClassOne Equipment based in Atlanta, GA, have experienced tremendous growth as more research institutes and universities, MEMS start-up companies and FABs are realizing they can save big by buying refurbished semiconductor equipment. With a turnkey solution that includes full refurbishment to OEM specs, installation and training, and an industry-leading 6-month warranty on parts and labor with a 30-day return policy, ClassOne is a leading supplier of refurbished equipment from the top manufacturers – Suss Microtec, KLA-Tencor, EVG, and Semitool to name a few – at a price up to 65 percent less than the cost of new. With that level of savings, it’s easy to see why high-quality refurbished tools are becoming a more popular choice.  

To discuss the numerous benefits of refurbished equipment, please visit us in Booth #741 and be sure to join us for a complimentary cocktail on July 12 from 3:30 – 5 p.m. Please visit us anytime on the web at www.ClassOneEquipment.com

Horiba Semiconductor, a leading manufacturer of high precision-sensors, instrumentation, controllers and analytical equipment used world-wide in Semiconductor as well as Solar, Process, Automotive, Medical, Environmental, Chemical, etc. is pleased to be exhibiting at SEMICON West and Intersolar 2011.

Horiba has long been the leading provider production-proven solutions for wet chemical process monitoring to the global semiconductor industry and continues to harness its core technological competencies to develop innovative new solutions to meet the continually evolving needs of leading-edge device manufacturers worldwide.

Products featured at SEMICON West 2011 include Horiba’s industry-standard CS Monitor for measuring mixed chemical solutions along with monitors for optical monitors for O3 and dilute H2O2, a wide range of resistivity, conductivity, and conductivity-based concentration monitoring for a wide range of chemicals and pH monitors. Horiba is continually striving to offer product enhancements and develop next-generation products to meet the requirements of leading edge manufacturers.  These include monitoring of ultra-dilute chemical solutions, 4-5 component chemical solutions, monitoring for on-the-fly-mixing and sensor for pb level dissolved O2 monitoring of chemicals. Come by our booth #1819 in the South Hall to learn more about these and our other innovative products designed to improve your process.

On display at Intersolar (Booth # 5426) will be Horiba’s monitoring solutions to meet the unique requirements of solar cell manufacturers. These include monitors for a variety of etchants and their associated by-products.

Due to its continued technological innovation, Horiba will continue to be the leader in Semiconductor process monitoring solutions.

Third-Generation Precursors Enable Advancement

Applied Materials announced on July 12 that it has integrated chemical-vapor deposition (CVD) and UV-cure steps to reduce the dielectric constant (k) of multi-layer interconnects on 22nm node chips. Using a new organometallic precursor for porous CVD, the “Black Diamond” brand name has been extended to the ultra-low k (ULK) level as low as 2.2 for the final film. However, like all ULK films, the as-deposited film requires an ultra-violet (UV) cure to stabilize the pores, so the company has also upgraded the “Nanocure” chamber that also runs on the “Producer” hardware platform.

Increasing the porosity of the dielectric helps reduce its k value, but also renders the film susceptible to downstream plasma damage or physical damage during packaging steps.

Applied Materials says that the generation three precursor uses a patented molecule where the pore is grafted to the organometallic backbone. This seems to be a version of the molecular pore stacking (MPS) CVD processes that have been touted by Fujitsu and NEC at technical conferences in recent years. Using MPS, the maximum porosity is built-in from the “bottom-up,” instead of having to control porosity from the “top-down” like Black Diamond 2 low-k films using multiple precursors and chamber parameters. The company is attractively pricing the purportedly proprietary precursor. “The chemical cost per wafer will be equal or less than Black Diamond 2,” said Russ Perry, global product manager for dielectric depositions for Applied Materials, in an interview with the SEMICON Show Daily.

The upgrade to the UV-cure chamber includes newly designed optical and chamber components plus real-time UV intensity monitoring that improves yields. AMAT claims that 22nm node processing will require post-processing steps at the interface layers within the on-chip multilevel interconnect stack, as well as to the ULK material to improve mechanical properties. The result is a dramatic increase in the number of UV-cure steps needed in a logic manufacturing process flow, up to supposedly greater than 49 UV cure steps at 22/20nm.

– Ed Korczynski

Industry Investing More in The Upcoming Transition

Top equipment vendors are stepping up their efforts to develop 450mm equipment, with significant R&D spending starting to occur, said presenters at different SEMICON sessions.

“We can’t ignore 450mm,” said Rick Hill, CEO of Novellus Systems. The R&D engineers at Novellus are dealing with plasma uniformity issues and other core topics, he said, but work is going forward.

“Clearly, there is a communication going on (about 450mm). Our customers know that everyone has got to be able to make a buck,” Hill said.

Mike Splinter, CEO of Applied Materials, said “450mm is at least two nodes away. There is still a lot of work to do.”

A securities analyst asked Splinter how much Applied will spend next year on 450mm equipment development. He was reluctant to put a specific number on Applied’s plans, but said 450mm-related spending is likely to exceed $100 million next year. That comes out of what a spokesman said is roughly a $1 billion-dollar R&D budget.

Randhir Thakur, general manager of Applied’s Silicon Systems Group, said the 450mm related investments by the major customers “are going forward.” Applied has learned to keep in close communication with those customers so it doesn’t get ahead or behind their curve.

At Novellus, Fusen Chen, the executive vice president in charge of semiconductor systems products, said Novellus is not going to be a bottleneck for its customers. None of the technical challenges brought by the larger wafers are unfamiliar to the Novellus R&D staff. During the 300mm wafer transition, customers stopped and started their 300mm transitions three different times. Then, when the 300mm tools started shipping, equipment companies found that customers were paying a small premium for tools that cost much more to build. Material costs were higher for the 300mm equipment, and in some cases one tool would replace several 200mm tools.

“All of the technical issues are within our areas of expertise,” Chen said, adding that the key challenge involves the return on investment.

– David Lammers

3D Structures and Stacking Lead to New DFM

There are incredible changes sweeping the industry as leading-edge commercial fabs begin to ramp 22nm node chips. Partially-depleted planar transistors in bulk silicon have been used for the last 50 years, but must finally be replaced with fully-depleted (FD) channels. Both 3D multi-gate/“finFET”architectures and SOI (FD-SOI) wafers can full-deplete channels, however, so these technologies seem mandatory for logic and mixed-signal SOCs in the near future. Stacking chips in 3D using through-silicon vias (TSV) is being done in multiple pilot lines. Managing all of this new 3D requires new tools and methodologies in design for manufacturing (DFM). 

The hundreds of interdependent process steps that must be controlled in a modern CMOS IC fab evolved in harmony over the last 50 years. Resolution limits of the old process flows, however, now require us to think in completely new dimensions. Patterning below the resolution limit of lithography requires the use of 3D stacks of sacrificial patterning layers along with the resolution burden being transferred to etch. Memory cells constrained by area move into the next dimension for storage nodes and transistor layouts.

With design and mask costs increasing, and with greater emphasis on consumer electronics demand surges that drive high-volume manufacturing (HVM) at advanced nodes, the cost of design failure becomes ever greater. DFM today can include design for test (DFT) and design for e-beam (DFEB) maskmaking to ensure that the first silicon reaches market.

3D Structures

Intel has announced that the “tri-gate” finFET will be the company’s 22nm transistor technology for high-volume manufacturing (HVM) of digital ICs. With much of the IC fab world focusing on low-power chips for mobile applications, the fully-depleted channels of finFETs provide reduced power consumption. However, there are 2nd-order electrostatic issues associated with the 3D structures so that new possible leakage paths must be controlled. Intel’s use of finFETs is also noteworthy because both compressive and tensile strain have been retained from planar devices. Meanwhile, leading commercial foundries TSMC and GlobalFoundries have both officially declared that they will not need finFETs until 16/14nm.

At IEDM 2010 (S05P03), researchers from North Carolina State University (NCSU) working for Intel and the National Science Foundation (NSF) demonstrated that properly engineering sandwiches of Hf-based high-k dielectrics — in combination with TaN metal floating- and control-gates — reduce gate-to-gate leakage, allowing NAND Flash scaling down to 1Xnm nodes. DRAM can be extended to 22nm node and smaller by using ALD and extensions of other deposition technologies that provide conformality in forming MIM stacks inside of extremely high aspect-ratio (AR) structures.

3D Stacking

Through-silicon vias through ICs (TSV-IC) have been in R&D for over 10 years and are finally scheduled to reach commercial use in IC manufacturing this year. Vias will be made through silicon in DDR3 DRAM dice to reduce size and power consumption for mobile devices, as scheduled for sampling by Elpida in the 2H11. Typical TSV-IC processes have used 5:1 to 10:1 ARs for chips 10 to 50µm thick.

TSV through interposers (TSV-interposer) will be made by many outsourced test assembly and packaging (OTAP) fabs. For interposers, the final silicon target thickness will be 100 to 140µm. Interposer thickness cannot be reduced below 100µm without rigid silicon wafers becoming flexible silicon foils.

Georgia Institute of Technology (GT) has a Packaging Research Center (PRC) working on TSV and 3D systems under packaging guru Rao Tummala. Professor Tummala has shown how to create the most cost-effective silicon interposers using panels of polysilicon instead of wafers of single-crystalline silicon. Starting with 200µm thick sheets, Tummala’s process uses lasers to drill vias and then a polymer deposition to form insulation.

On the afternoon of Tuesday, July 12, at SEMICON West, a paid workshop will be held at the Marriott Marquis hotel on SEMI Standards for TSV commercialization. Also on Tuesday afternoon, at the Moscone Center NorthOne TechXPOT, the SEMI Advanced Packaging Committee of the Americas hosts a free conference on “Heterogeneous integration with MEMS and sensors.”

On Wednesday morning, July 13, from 9:00 am to noon in the San Francisco Marriott Marquis hotel, SEMI/SEMATECH will hold a workshop on “3D interconnect challenges and need for standards.” On Wednesday afternoon, from 1:30pm to 5:00pm in the Moscone NorthOne TechXPOT, the SEMI Advanced Packaging Committee of the Americas will host “3D in the deep submicron era,” which includes Prof. Tummala as a panelist.

DFM

With the source wavelength for lithography stuck in water at 193nm, and all post-optical “next-generation lithography” (NGL) technologies still stuck in R&D, the only way today to form 32nm and smaller structures is to use clever extensions to optical litho like double-patterning (DP) and source-mask-optimization (SMO). Such extensions require integration of design and manufacturing technologies to an ever greater extent. DFM is only possible with accurate fab data, so to design ever-smaller devices, the industry needs ever more capable measuring tools.

Electron-beam (e-beam) lithography has long printed the photomasks used for chip production, but the best vector-scanned e-beam writers can still take ~80 hours to write a single mask at the 22nm node. Design for e-beam (DFEB) along with cell projection e-beam exposure tools can reduce the time needed to write a 22nm-node mask to <30 hours, according to the e-Beam Initiative.

On Wednesday morning, from 10:30am to 12:45pm in the Moscone NorthTwo TechXPOT, SEMI will host back-to-back “Design and Manufacturing” panels: yield improvement methodologies, and the influence of 2.5/3D chip stacks on the global supply chain.

–Ed Korczynski

Exploring Technologies for Ultimate Phones

IMEC, the international micro-electronics R&D center in Leuven, Belgium, held a technology forum in the afternoon of July 11 to discuss enabling technologies and supply-chain infrastructure issues associated with future “Smart Phones.” Presentations included reviews of the market requirements from the perspectives of Intel and Qualcomm and recent technology developments at IMEC.

Smartphone applications have rapidly become the main force driving new technologies in semiconductor manufacturing. Mobile and low-power applications now drive both the leading edge of R&D and high-volume manufacturing (HVM), replacing the personal computer that led applications in recent decades. The trend toward ever-more integration of functionalities into mobile devices seems irreversible, with sensors for proximity, light, and touch already combined, along with gyroscopes and accelerometers.

Justin Rattner, Intel chief technology officer (figure), explained that our phones will soon be “smart” enough to be aware of our location in the world and what information we would like automatically delivered to us. In addition to ‘hard’ sensing of direct physical information, Rattner’s group also works on “soft” sensing of your calendar and browsing trends as another way to constantly learn about us. “We’ll be able to use skin response and heart rate to be able to infer your mood, so if you’re having a difficult day, your devices may go easy on you,” explained Rattner.

Robert Gilmore, VP of engineering at Qualcomm, said that the future phone is expected to be “always on” in sensing and communicating with its environment. To minimize continuous battery draining, tight integration is needed between hardware and software. IMEC has been working on ways to make each transistor less leaky as part of “More Moore” efforts, as well as on ways to integrate new sensors with CMOS as part of “More than Moore.”

– Ed Korczynski