Secondary Equipment Market’s Secret Life

Analysis: Why the used equipment market has suddenly become so robust and why everyone needs to understand power and the importance of stacked die.

For almost as long as anyone in semiconductor manufacturing can remember, the used equipment market has always been associated with second-tier chipmakers and fabs. They lived in the backdrop, away from the perpetual battle to stay out in front of Moore’s Law, where the only differentiator was the price of hardware.

Out of the gate, the equipment was depreciated, but the processes were generally well defined because they had been in use for at least several years and the markets well understood.

Four significant shifts are altering that perception:

1. Power. At almost every process node, there are now low power and super low power processes being created. That has added new life into processes all the way back to 180nm, and in some cases even beyond. For many applications, if there is sufficient cost savings at older nodes with a concurrent increase in energy efficiency, then the chips being produced using older processes can be competitive in many cases.

2. Not everything scales. Analog developers have been complaining about migrating their technology to the most advanced nodes for years, which is one of the big attractions of stacked die. The most advanced nodes for analog are actually 40nm, while the largest volume of analog is somewhere between 90nm and 130nm. New equipment is not required for these technology nodes.

3. Costs for leading-edge fabs are exorbitant. The other piece of the equation is the sheer volume needed for foundries to stay on the leading edge. With the most advanced fabs now costing up to $5 billion, very few companies can afford to keep up. Even most of the IDMs now utilize a foundry model for the same reason.

4. New markets do not necessarily require new equipment. MEMS, photovoltaic and LEDs, in particular, are hot and growing markets that do not rely on the most advanced equipment. In fact, much of the manufacturing is done at older nodes using smaller wafer sizes.

“The secondary equipment market is a key contributor to the success of manufacturing,” said Karen Savala, president of SEMI Americas. “There are a lot of 200mm and 300mm fabs that rely on secondary equipment sourcing. This has been a way for some of the key equipment suppliers to come back to SEMICON.”

– Ed Sperling

Strong Industry Growth Buoys SEMICON West

SEMICON West is experiencing a rebound from the past couple of years, with a nearly 10 percent increase in booths and several hundred companies demonstrating real products on the show floor.

Speaking at a Monday SEMICON West press conference, Karen Savala, president of SEMI North America, called the improved attendance a “modest recovery” from the 2009 to 2010 period, which she said “hit the exposition industry hard.”

The concurrent Intersolar North America show is now roughly the same size as SEMICON West. Savala said Intersolar N.A. is expected to enjoy 18 percent growth this year, with 662 exhibitors. SEMICON West is expecting 711 exhibitors this year. About 30,000 attendees are converging on San Francisco for the semiconductor and solar equipment and materials shows, she said.

SEMICON West’s improved fortunes are being driven by forecasts of “pretty strong growth in the semiconductor market” for the next few years, SEMI executive vice president Jonathan Davis said. Demand for semiconductor equipment and materials will likely be “steady as she goes” for the next year or two, after a strong rebound in 2010.

Davis, president of SEMI’s semiconductor business operation, said the semiconductor industry is likely to increase from $314 billion this year (the first year that chip revenues are expected to exceed the $300 billion threshold) to $375 billion in 2014, according to the World Semiconductor Trade Statistics (WSTS) council. That will drive “steady growth in fab capacity,” including continuing investments in North America by Intel, GlobalFoundries, and Samsung Austin, among others, Davis said.

While SEMI is predicting a 19 percent increase in wafer fab spending this year, a cyclical decline in spending by the test and assembly sector will drag down the total, resulting in a 12 percent increase in overall equipment spending this year. Of the $44.3 billion in expected equipment spending, a respectable $9 billion will be in North America, exceeded only by Taiwan’s spending. Dan Tracy, director of SEMI’s Industry Research and Statistics operation, said the test forecast depends partly on the “wild card” of investments by the memory IC vendors.

Next year could see “some slight cuts” in overall fab equipment spending, a predicted 1.2 percent decline, Davis said. The materials sector, driven by strong unit growth, will continue to grow by $2 billion, from $46 billion this year to $48 billion next year.

At a Monday market briefing by market research firm Gartner Inc. and SEMI, Gartner research vice president Dean Freeman said the rest of 2011 will be buffeted by concerns over oil prices, sovereign debt, jobs, and housing. “Oil drives our economy,” Freeman noted, adding that “no one is putting many bets on the second half of this year, but 2012 should be stronger.”

The 41st edition of SEMICON West comes as longtime CEO Stanley T. Myers plans to retire later this year from executive management of the worldwide trade association he has led for 15 years. SEMI board chairman Doug Neugold, CEO of ATMI Inc., said Myers was a “culturally sensitive, positive, and excited” leader during his years as SEMI’s chief executive.

Neugold said as the search continues for a new chief executive, the board will work this year and next to re-evaluate SEMI’s organization. “This is an important year in the evolution of SEMI,” he said.

Leo Berlinghieri, CEO of MKS Instruments, is the SEMI board member leading the association’s initiatives in Washington, D.C. “At a time when the discussion in Washington is about cuts, cuts, cuts, it is sometimes hard to get our messages across,” Berlinghieri said.

Funding for the key U.S. research labs is “slipping compared with the rest of the world.” And he called for more H1B visas for scientists and engineers educated in the U.S., some of whom are forced to leave the country after completing their educations. Though Congress continues to renew the investment tax credit, Berlinghieri said Washington should make the tax credit permanent.

SEMICON West continues to broaden its focus, with more attention paid to LEDs, MEMS, printed and flexible electronics, and the needs of the fabless and fab-lite semiconductor companies. The show will include more than 100 hours of technical sessions, including TechXPOTs on lithography, new logic and memory device types, advanced packaging, MEMS, and other emerging markets.

– David Lammers

Fab Challenges for 22nm Include FinFETs and Emerging Architectures

The imminent switch to a vertical transistor by the world’s largest semiconductor company – after 50 years of planar ICs – has experts gauging the impact of Intel’s fully depleted tri-gate announcement on the wider semiconductor industry.

Will foundries such as TSMC accelerate their plans for a finFET-based technology platform at the 16/14nm node? (As one equipment executive put it: “The big fabless companies already are asking their foundry partners: ‘When do I get my finFET?’”)

Will some companies prefer an ultra-thin-body planar SOI platform, believing that yields will be higher, costs lower, and power consumption as good as that of finFETs? Will companies such as IBM, which has an embedded SOI DRAM, use SOI wafers for a finFET architecture? And will startup SuVolta, with its claims to a low-power technology in a bulk (non-SOI) planar CMOS, garner adherents?

These questions will arise this morning (July 12) at the Emerging Architectures for Logic and Memory TechXPOT, planned for 10:30am to 12:30pm in the North Hall of the Moscone Center. To be sure, by the 16/14nm node the industry will shift to a fully depleted architecture for improved short channel control and less sub-threshold leakage, said Serge Biesemans, vice president of process technology at IMEC and one of the speakers at today’s TechXPOT.

FinFETs with a fully depleted channel, Biesemans said, turn on faster, allowing companies to target a lower threshold voltage, delivering higher drive current and faster circuit speeds. Intel claims that its 22nm tri-gate will be 37 percent faster than its 32nm planar transistor at 0.7 V_dd. That may allow Intel to run its 22nm MPUs at a V_dd of about 100 to 200 mV less than its 32nm processors, providing a 50 percent power savings at the device level.

Manufacturing Challenges

The advantages of finFETs depend on solving several manufacturing challenges, ranging from lithography to implants to etching and beyond. Indeed, University of California at Berkeley professor, Chenming Hu, argues that in the early going only the deep-pocketed companies such as Intel, TSMC, and one or two others may be able to deliver finFETs at acceptable yields.

With finFETs, the height of the fin is equivalent to the channel length, and the fin width must be kept to half of the fin height. Controlling these two dimensions precisely is one process challenge.

Kaizad Mistry, the 22nm program manager at Intel’s Technology and Manufacturing Group in Hillsboro, Ore., said a skinnier fin is needed to provide the fully depleted behavior, as well as to control short channel effects. However, “if the fin is too skinny, then current resistance gets larger. Too wide, and we don’t get nice fully depleted behavior,” he said.

There is a similar tradeoff for the fin height. A taller fin delivers more drive current, but at a higher gate capacitance. “It depends on the type of circuit, whether it has more interconnect load or more transistor load,” Mistry said.

Because the narrow fins are undoped, said Biesemans, work function engineering (WFE) depends primarily on dual-WF high-k/metal gate steps. And the narrow fins are difficult to recrystallize, requiring adjustments to the annealing steps. Source and drain regions present new challenges: selective epitaxial growth on the undoped fins require careful implants in the source and drain regions, he said. Strain engineering on the vertical transistors requires other changes.

Solutions Matter

How companies solve these issues will dominate the technology agenda for years. FinFETs based on silicon channels may share the stage with UTB-SOI at the 16/14nm and 12/10nm nodes. Beyond that, researchers may try to bring in higher-mobility channel materials, perhaps introducing silicon germanium in the pFET and III-V materials in the nFET, on either vertical or planar structures. Raj Jammy, Sematech’s VP of materials and emerging technologies, will discuss these heterogeneous technologies at the Emerging Architectures TechXPOT. The third speaker will be Ali Khakifirooz, the ETSOI lead device engineer at IBM Research.

And what may be doable for Intel, with its ability to dedicate fabs to just a few mask sets, may be a much tougher manufacturing challenge for foundries. “The biggest challenge with the tri-gate technology is to have a robust manufacturing process, to pattern the fins with the required fidelity of the fin width and height, and do it for billions of transistors,” said Mistry.

Hu, who led a Berkeley team that proposed a workable finFET a dozen years ago, said “initially, these transitions are going to be so very difficult, but if the right amount of time, money, and people are invested, they can get it done.”

– David Lammers

GaN Strains to Integrate with Silicon

With applications from automotive instrument panels to efficient room lighting, high-brightness LEDs have become an important manufacturing segment over the last few years. Strategies Unlimited, a market research firm, estimated HB-LED sales of $10.8 billion in 2010, nearly double the 2009 figure. Thirteen of the 17 high volume fabs that SEMI expects to begin construction this year are LED fabs.

General lighting is an extremely cost-sensitive sector. As Rainier Beccard, VP of marketing at Aixtron (Aachen, Germany), explained, “MOCVD reactor capacity remains the key parameter with the strongest influence on [fab] operating cost.”

As in the integrated circuit industry, increasing either the wafer size or the number of wafers processed per reactor cycle can dramatically reduce the cost per device. To that end, Aixtron’s newly introduced CRIUS II-L MOCVD (photo, left) reactor can accommodate 16 4-inch or 69 2-inch substrates, which the company claims is the largest capacity available in a manufacturing-proven reactor. Moreover, the company said, the reactor design is optimized for wafers up to 8-inches in diameter, offering even more potential for productivity improvement.

Actually producing high-quality 8-inch substrates is another matter, though. The GaN material used to produce blue and green LEDs has a substantial lattice mismatch with silicon (table, below). It is usually grown on sapphire or silicon carbide substrates, but even those materials introduce lattice mismatch defects that ultimately limit the performance and efficiency of HB-LEDs. While combining GaN-based LEDs and silicon-based integrated circuits into a single device could cut packaging costs and reduce the total system footprint, such structures are not easy to realize in practice.

Table: Lattice mismatch and GaN

 Substrate                                  Lattice constant (Å)                 Mismatch vs. GaN

GaN                                           3.19                                         —

GaAs                                         5.65                                         77%

Al₂O₃                                         2.75 (sublattice)                      -14%

SiC                                            3.09                                         -3%

Si                                               5.43                                         70% 

Manufacturers have several options for managing the large mismatch strains between GaN and silicon. One approach avoids the question entirely: the Soitec (Grenoble, France) SmartCut process, used to produce most commercial silicon-on-insulator (SOI) wafers, can also transfer an epitaxial GaN layer to a silicon substrate. This method could be used for 3-D integration, stacking an HB-LED array on top of a complete silicon integrated circuit. Unfortunately, the cost of the SmartCut process has limited acceptance of SOI wafers, even for high-value integrated circuits. Cost-sensitive commodity lighting suppliers are likely to be even more wary.

Alternatively, a series of buffer layers, each with a slightly different composition and lattice constant, can produce a gradual transition from the silicon to the GaN structure. This method is used for GaN deposition on sapphire or silicon carbide, but clearly a much thicker buffer structure is needed to manage the much larger mismatch between GaN and silicon.

Furthermore, according to Lattice Power (Jiangxi, China), the thermal expansion mismatch between the GaN buffer layers and silicon can still cause strain and cracking during deposition. The company’s design uses a pre-patterned substrate with trenches to keep cracks in one area of the wafer from propagating to the next. Though the silicon wafers used are still only about two inches across, Lattice Power claims to have achieved performance and yield comparable to sapphire-substrate LEDs.

While LEDs are discrete devices, GaN’s high breakdown voltage and good thermal conductivity are also of interest for advanced power devices. It can provide more efficient switching for wind turbines, electric vehicles, and other emerging energy technologies. These more complex devices would benefit from the silicon integrated circuit industry’s large manufacturing infrastructure.

The GaN-on-Si program at IMEC (Leuven, Belgium) seeks to deposit GaN-based materials on larger silicon wafers. Wafer supplier Siltronic AG (Munich, Germany) recently joined this effort, which already includes device and substrate manufacturers.

– Katherine Derbyshire

It’s Not Just the Dielectric

Low-k Meets Circuit Integration

One of the most important, and frustrating, lessons of the semiconductor industry’s long struggle with low-k dielectrics is the need to consider those materials in the context of fully integrated circuits. Results derived from test structures on blanket films may not extrapolate to actual circuits.

For example, the impact of packaging on the dielectric material is still not well understood. In 2006, regulations in the European Union prohibited the use of lead-based solders in consumer electronics. Alternative solders, often based on tin-silver-copper alloys, generally have higher melting points and require more bonding pressure. These parameters may lie outside the expected process space for integration schemes that were successful with lead-based solders.

Third-generation materials

Third-generation low-k dielectric materials give manufacturers additional flexibility to address constraints imposed by the circuit as a whole. As explained by Klaus Schuegraf, CTO of Applied Materials’ Silicon Systems Group second generation materials incorporated relatively large pores into dense carbon-doped oxide materials. Third generation materials, in contrast, still depend on carbon-doped oxides, but are based on new starting materials that incorporate nanometer-scale pores into the oxide’s molecular structure. In third generation materials, Schuegraf said, manufacturers can more precisely engineer porosity to achieve the dielectric constant and mechanical strength required by a particular integration scheme.

This control of the material structure gives process engineers new ways to address plasma damage as well. Plasma is used in both pre- and post-etch cleaning steps, as well as in the dielectric etch itself, and plasma damage has always been one of the most severe obstacles to low-k dielectric integration. Carbon depletion is one of the most notorious damage mechanisms, but the etch-clean cycle can also deposit residues on the dielectric surface, densify the dielectric material, and damage the sidewalls of features. If plasma damage is bad enough, the metal diffusion barrier may fail to adhere, allowing moisture and metal ions to infiltrate the dielectric. Even under optimum conditions, the damaged layer increases the effective dielectric constant of the structure. As device features get smaller, the damaged layer accounts for a larger fraction of the total linewidth, to the point where damage can offset the advantages of a lower dielectric constant.

Optimism

Still, the view within the industry is optimistic for dielectric repair processes to reverse the effects of carbon depletion. Unfortunately, most were reluctant to discuss specific repair schemes in any detail. Some alternatives have appeared in the open literature. For example, in work presented at MRS, Sven Zimmerman of Fraunhofer ENAS reported that methylation and silyation can both restore depleted carbon. His group immersed etched low-k materials in HMDS (C₆H₁₉NSi₂), finding that the Si-methyl groups bonded to the dielectric surface, while UV radiation helped to eliminate excess hydrogen. Other approaches depend on combinations of heat, optical treatments, and controlled atmospheres to extract incorporated moisture and restore the dielectric’s surface composition.

Timing

Timing is an important variable in any potential repair strategy. Since damage can occur at several points, up to and including the final cleaning step before deposition of the metal diffusion barrier, the repair step should be inserted into the flow as late as possible. On the other hand, any repair of the dielectric must be completed before deposition of the diffusion barrier, both to ensure good barrier adhesion and because deposition of the barrier will block any further changes to the dielectric.

In March, Novellus introduced the Lumier pre-treatment chamber for the company’s Vector Excel diffusion barrier deposition system. This chamber can provide heat treatment, optical treatment at a variety of wavelengths, and a controlled atmosphere, thereby supporting a number of potential pre-treatment strategies.  According to Easwar Srinivasan, Novellus’ director of product marketing for PECVD, the company has seen materials with as-deposited k=2.4 degrade to dielectric constants of 3.1 to 3.2 after etching. In internal tests, the company has been able to restore 70 to 80% of that damage. While similar numbers have been achieved in complete circuits, Boaz Kenane, director of technology for UVTP PECVD at Novellus, warned that the capacitance of fully integrated devices is difficult to measure, and actual RC constants may vary.

This brings us back to a central challenge of low-k integration: the impact of the rest of the device structure. Not only packaging, but also etch pattern dependencies and the characteristics of the copper lines all play important roles.

– Katherine Derbyshire

Industry Future Looks Solid, Says SEMI

The SEMICON Show Daily interviewed Jonathan Davis, president, Global Semiconductor Business, at SEMI, and asked for his perspective on the state of the global semiconductor business.

SEMICON Show Daily: What’s defining the semiconductor business today?

Jonathan Davis: The industry is going great – this is the first time the industry has crossed the $300 billion mark. We expect to see continued growth for the next three years, and we see investments not just in foundries for flash memory, but for the new technologies that are driving advanced devices.

The commitment to ongoing R&D investment is critical to this industry because new technologies are expensive to develop. In fact, they are so expensive now that alliances and consortia are the only way to continue this advancement, as few if any companies can alone expend the capital required.

SSD: What are the biggest issues facing the industry today, and how are they being addressed?

JD: There is a plethora of issues. There’s 3D — not only the movement to 3D device structures, but also the challenges of 3D packaging as it becomes critical to multilevel stacking and smaller die footprints. Both of these areas demand investment in R&D and innovation to bring them to market. Of course, next-generation lithography — EUV — is and has been a hot topic. The engineering that has kept current lithography techniques advancing far beyond what was expected is nearing its limit, so EUV investment is rising — but it’s a significant amount of investment. There’s also the transition to 450mm diameter wafers. Discussions on the transition began a number of years ago, but we’ve seen that it will be a very expensive one that needs a lot of forethought and planning to happen efficiently.

SSD: How big an impact is there from new personal computing and communicating devices, and have these offset the general worldwide slowdown in PC unit growth?

JD: I think the fascinating inflection point here is the development and adoption of tablets, pads and their technology. These products, with their global, local, and social capabilities, are changing the markets for computing products. The demand for semiconductor devices continues to rise worldwide; any slowing of growth in one area is usually offset by a rise in another. We’re seeing the prospect of continued growth – even improved growth – in emerging markets, and we expect the number of transistors sold each year to continue to increase.

SSD: The SEMI book-to-bill ratio was above 1.0 from July of 2009 to September of 2010, but it has slipped back under 1.0 for the eight months since then. Is this a cause for concern?

JD: No, not at all. The book-to-bill ratio, released each month by the SEMI Industry Research and Statistics group, was well above 1.0 for the period you mentioned because the entire industry had restrained its capital expenditures before then. This run of positive book-to-bill numbers reflected the pent-up demand that existed for equipment and the need for fabs and foundries to continue their technology and capacity investments.

The recent book-to-bill numbers are just under 1.0, which reflects a near-steady state of balanced resources and investment, and it also reflects the time needed for the industry to absorb the capital equipment they purchased during the mid-2009 to mid-2010 timeframe.

SSD: What lasting effect has the earthquake and subsequent tsunami that struck Japan on March 11, 2011, had on the semiconductor manufacturing industry?

JD: First, the earthquake and tsunami that devastated the Tōhoku area of Japan in March was a terrible human tragedy. We’re proud that SEMI staff, SEMI members, and friends raised over $50,000 for the SEMI Japan earthquake relief fund, all of which went directly to help those afflicted.

The semiconductor industry has recovered well. The majority of the semiconductor processing facilities in Japan were unaffected, but supply chains did get adjusted as manufacturers worked though inventory, relied on second sources, and spread their production and mixes across their global facilities. Japan is the world’s largest producer of chips, and the world’s largest market for semiconductor manufacturing equipment, so there was the risk of serious global disruption, but that has not come to pass.

And importantly, the semiconductor industry is one that learns — and spreads information – quickly. Lessons learned — from preparedness, to infrastructure rethinking, to second sourcing optimization — have already been implemented. Companies have been more than willing to share knowledge, advice, and best practices information around the world to ensure that they are prepared as possible when another natural event happens.

Horiba Semiconductor, a leading manufacturer of high precision-sensors, instrumentation, controllers and analytical equipment used world-wide in Semiconductor as well as Solar, Process, Automotive, Medical, Environmental, Chemical, etc. is pleased to be exhibiting at SEMICON West and Intersolar 2011.

Horiba has long been the leading provider production-proven solutions for wet chemical process monitoring to the global semiconductor industry and continues to harness its core technological competencies to develop innovative new solutions to meet the continually evolving needs of leading-edge device manufacturers worldwide.

Products featured at SEMICON West 2011 include Horiba’s industry-standard CS Monitor for measuring mixed chemical solutions along with monitors for optical monitors for O3 and dilute H2O2, a wide range of resistivity, conductivity, and conductivity-based concentration monitoring for a wide range of chemicals and pH monitors. Horiba is continually striving to offer product enhancements and develop next-generation products to meet the requirements of leading edge manufacturers.  These include monitoring of ultra-dilute chemical solutions, 4-5 component chemical solutions, monitoring for on-the-fly-mixing and sensor for pb level dissolved O2 monitoring of chemicals. Come by our booth #1819 in the South Hall to learn more about these and our other innovative products designed to improve your process.

On display at Intersolar (Booth # 5426) will be Horiba’s monitoring solutions to meet the unique requirements of solar cell manufacturers. These include monitors for a variety of etchants and their associated by-products.

Due to its continued technological innovation, Horiba will continue to be the leader in semiconductor process monitoring solutions.

Mattson Technology today introduced the paradigmE® Si for semi-critical silicon etch applications. The latest silicon etch system reinforces the new etch standard created by Mattson Technology’s production-proven paradigmE, which enables customers to meet stringent processing requirements for device manufacturing at leading-edge technology nodes. Multiple paradigmE Si systems are already in customer production.

Built on the paradigmE product architecture, paradigmE Si incorporates enhancements to enable customers to run the chemistries required for poly-silicon applications. The system features Mattson Technology’s proprietary Faraday shield designed to improve etch process control and enhance mean-time-between-clean (MTBC) performance by up to three times over competitive systems. The paradigmE Si also enables true independent control of ion density and energy, providing improved profile control and minimized sputtering to reduce maintenance costs for the lowest cost-of-ownership.

“Customers currently use critical poly etchers to run semi-critical applications—this tool-application mismatch results in a higher cost of ownership,” said Rene George, vice president and general manager of Mattson Technology’s Plasma Products Group. “The paradigmE Si is specifically targeted at semi-critical poly etch applications by providing excellent process performance with over 30% better cost-of ownership advantages over any competitive etch system currently on the market. The introduction of this latest tool to our etch portfolio enables us to serve approximately 30% of the growing silicon etch market, broadens our etch application set and expands our total served available market by over $500 million.”

For more information, contact Mattson at www.mattson.com

Receive immediate cash and/or trade-ins for idled equipment

ClassOne Equipment, a leading supplier of refurbished semiconductor equipment and sponsor of SEMICON West 2011, is aggressively seeking to purchase idled or surplus semiconductor process, metrology and inspection equipment. Companies with equipment for sale or trade should stop by Booth #741 or contact Dave Pawlak, Purchasing Manager, at 760-525-8990. Equipment lists can also be emailed to [email protected].

The following is a sample of the types of equipment ClassOne would like to purchase. Please note this list is not all-inclusive.

Process Equipment:

• ·         Suss, EVG, OAI, or other Mask Aligners
• ·         Suss or EVG Wafer Bonders (any model)
• ·         STS, Oxford, or Plasmatherm Etchers
• ·         Semitool SRDs
• ·         Semitool Wet Process Equipment
• ·         Wet Benches
• ·         Disco or ADT Dicing Saws or Grinders

Metrology Equipment:

• ·         KLA Surfscans (6xxx, SP1 Series)
• ·         KLA 2135, 2138, or 2139
• ·         KLA AIT XP+, XUV
• ·         KLA Flexus 2320
• ·         KLA Profilers (P10, P11, P22, P240)
• ·         KLA UV-1280 or F5x
• ·         Hitachi S8840 and S-9220 CD-SEM
• ·         Hitachi S-4700 SEM
• ·         ADE 9500 or 9700
• ·         Veeco Dimension 3100 AFM
• ·         Zeiss Axiotron Microscopes (or Olympus, or Nikon Microscopes)

To discuss any opportunities involving the sale or trade of surplus equipment, please visit Booth #741 or join us for a complimentary cocktail on July 12 from 3:30 – 5 p.m. You can also contact Dave Pawlak, Purchasing Manager, at 760-525-8990 or email an equipment list to [email protected].

MonolithIC 3D

New fabs now cost upwards of $5B. Advancements in lithography and other process steps are so expensive as to demand multi-company collaboration to reduce risk.

Perhaps the era of scaling down is coming to an end, and perhaps the era of building up is just beginning.

That’s the premise of MonolithIC 3D, a company with the idea – and the technology – to build vertically. Building up is not new; the industry has been expecting 3D for decades, and is now starting down that path with through-silicon-via (TSV) technology.

But MonolithIC 3D thinks they have a better approach, and that’s how the company became a finalist for the SEMICON West 2011 “Best of West” Award.

Company founder Zvi Or-Bach, who previously started Chip Express and eASIC, says that TSV technology is certainly a reasonable approach, but that building layer upon layer of chips would be better. Current silicon processing techniques, with the need for 1000° C temperatures for silicon dioxide growth, preclude creating one “level” of a chip and then building another above it. Since the only other way to build “up” today is TSV, that’s where engineers are working.

TSV is completely appropriate for finished devices, says Or-Bach, but there may be a better way to accomplish the vertical construction that will lead to high-density transistor stacking.

MonolithIC 3D’s approach is to start with a conventional wafer with transistors and layers of copper interconnects. Then, a bilayer stack of p- Si and n+ Si on a separate new wafer is constructed using implant and epitaxial processes, and the dopants on the new wafer are activated with normal high-temperature techniques. Next, hydrogen is implanted into the new wafer with p- and n+ Si regions to create the “cut” or “shear” plane. That new wafer is then flipped and oxide-to-oxide bonded atop the first wafer. The stacked wafers are then cleaved at the hydrogen plane, leaving the thin doped layers of mono-crystalline silicon atop the bottom wafer.

Then “Recessed ChAnnel Transistors (RCATs)” are formed using etch, deposition and other processes typically conducted at <400° C. The gate dielectric and gate electrode are deposited with atomic layer deposition (ALD). Finally, interconnects between the layers (and above the transistors at the second wafer layer) are built.

According to Or-Bach, this process flow has three unique – and necessary – characteristics: The process steps for transistors that require >400° C, such as implant activation, are done before the wafer-to-wafer layer transfer, ensuring thermal budget compatibility with the copper interconnects of the lower wafer. Recessed channel transistors (that allow a transistor to be defined with sub-400C processes such as etch and deposition, are used for the upper layers. And finally, the layer to layer interconnect for the 3D stack is accomplished at close to full lithographic resolution and alignment.

Or-Bach notes that MonolithIC 3D has approaches for the distinct differing needs of logic, DRAM, NAND, and other silicon device processing.

This is intriguing technology, and it is an approach that could define the next direction of transistor production for a long time. With standard scaling costs becoming prohibitive, building up is the logical approach. MonolithIC 3D’s approach allows a designer to build levels upon levels of transistors, which is much more flexible, cost-effective, and open than the TSV approach of stacking and connecting finished die.

MonolithIC 3D is at SEMICON West 2011, Booth 5585, and at MonolithIC3D.com