Chemical mechanical polishing (CMP) has increasingly been recognized as an enabler for the fabrication of novel structures for MEMS and optoelectronics devices. Many of these applications require ultrasmooth surfaces and/or planarization of unique layers in order to function properly, and CMP is the only process capable of delivering the desired result.

Examples include planarization of thick oxides for MEMS, final step polishing of strained-layer germanium or SiGe structures, and surface roughness reduction for GaN, sapphire or other ultrahard materials. In many cases, determining the right combination of CMP consumables (pads and slurries) and tool process conditions is a major challenge, particularly when incoming surface conditions add to the variables that need to be understood before a successful process can be defined.

During the latest slowdown in the industry, the MEMS/optoelectronics market, as a whole, was outpacing the general market in revenue growth rate and R&D activities. New trends in MEMS and optoelectronics manufacturing are driving the need for CMP, but pose unique polishing challenges. MEMS require polishing of thicker oxide and polysilicon films and other non-CMOS materials. The polishing times for the thicker films and larger step heights can be significantly longer, meaning that process stability and consumable lifetime need to be monitored and addressed. Specialized slurry formulations are not always commercially available to create optimal polishing conditions to control removal rate, non-uniformity and defects, posing another challenge for process engineers.

Many of the new materials being integrated show non-linear polishing behaviors, while epi materials grown with lattice mismatch to the underlying layer are likely to require polishing to reduce surface roughness. For example, GaN epi can be grown on sapphire, transferred to another substrate, polished and the process is repeated. Low roughness, minimum defects and no contamination must be achieved or device parametric degradation can be realized. This is especially true for devices requiring direct wafer bonding (DWB). DWB require surfaces below 1 nm roughness, and CMP continues to be the best method to achieve this surface. Many TEOS surfaces encapsulating the new structures and materials can have an incoming surface roughness of >500 Å, but with an optimal process, a 3-10 Å final surface roughness can be achieved.

The success criteria for the CMP process for MEMS and optoelectronics manufacturing remains similar to that of semiconductors by understanding the following: film stack composition, layer thicknesses, incoming topography and post requirements, feature sizes and pattern densities, target thicknesses and uniformity requirements. Concerns that have resurfaced with the new materials and applications are film stress, mechanical integrity and delamination issues. By understanding the chemical interactions and process dynamics, solutions are able to be successfully implemented with the CMP process into novel devices, thereby enabling their functionality and accelerating their arrival into the marketplace.

— Jim Mello, Vice President of Sales/Marketing, Entrepix Inc.

Andy Bryant, executive vice president, technology, manufacturing and enterprise services and chief administrative officer, Intel“No one does it alone anymore, not even Intel.” In one of his closing lines from his keynote address on Wednesday, Andy Bryant, executive vice president, technology, manufacturing and enterprise services and chief administrative officer for Intel, explained that although consolidation has positioned the industry behemoth ahead of competitors, the company still needs to be agile and aware of what’s happening in the market and with competitors. Bryant, who has worked at Intel under four different CEOs, including the legendary and colorful Andy Grove, revealed some of the thinking that goes on there.

Bryant repeatedly emphasized the importance Intel places on technology and innovation and how if as a company you’re not innovating, you’re falling behind. The recent recession was a precarious time for the industry and was the wrong time to cut back on innovation, Bryant said. “You don’t save your way out of a recession.” He stressed how important it is to come out every year with better technical products and features. “If you’re not innovating, you’re falling behind.”

Bryant shared the company’s investment mandate:

• It is not enough to survive.
• We must move ahead and continue to thrive.
• We do this through efficiencies and continued investments in valuable technologies and people.

The company achieves this, Bryant said, by moving technology forward and adapting to the constantly changing business models, like several years back when gigahertz took a back seat to power consumption.

A key tool that has helped Intel remain agile during volatile times is supply chain excellence. The company was able to reduce its fab cycle time by 65%, which made it able to react more quickly to market fluctuations. Bryant said Intel increased its response time to customers by a factor of 3×, which made changing or canceling orders much more realistic. By reducing its inventory, the company was also able to not have as much capital tied up in finished product.

Other tips Bryant offered in down times were to attack non-essential spending and to proceed with investments that make the company more competitive. “Having money doesn’t get you a solution,” Bryant said. “Many of Intel’s businesses failed, I think, because they were given too much money.” If they were given a tight budget and forced to innovate, chances are they might have succeeded.

Bryant admitted the major costs involved with having a factory and said a company needs about $10 billion in revenue per leading-edge fab it supports. This obviously limits the number of players in the industry, especially since R&D continues to grow in expense as well as a percentage of a company’s revenue. The integrated model, however, works for Intel, and Bryant said it’s because everybody works for the same owner, there is a more thorough transfer of knowledge, and there is more agility under that model. This leaves smaller players left with collaborative efforts, a practice Bryant fully supports. “With more companies seeking to collaborate and integrate,” he said, “value flows back and forth through market segments.”

To clarify, Bryant said that the industry itself isn’t consolidating as an industry, but the businesses within it are. Regardless, opportunities for growth remain significant, with potential gains in the automotive, government and healthcare industries, he said.

“Growth is going to continue,” Bryant said. “The question is, how are we going to adapt to it?”

— Arthur Patterson, SEMICON West Daily News

The need for new memory structures, such as resistive RAMs (RRAMs), and through-silicon vias (TSVs) are presenting formidable materials challenges, speakers said at Wednesday’s TechXPOT on Advanced Processing and Materials.

There are “strong fundamental reasons” why RRAMs may emerge as a viable non-volatile memory, replacing floating gate flash at some point, said Paul Kirsch, director of front-end processes at Sematech. Memory researchers are investigating cross-bar arrays of RRAMs, which feature low power consumption at the bit level. With RRAMs also offering the prospect for low-cost processing, the memory could be embedded on SoCs or used in standalone memories. Kirsch noted that over the rest of this decade, high-end SoCs will be dominated by on-chip memory, with logic transistors accounting for 5% or less.

The RRAM research effort is focused on identifying the correct metal oxides, with nickel oxide as one of the promising materials to form the metal filaments that represent a memory bit. Etching and cross-contamination are major challenges. PVD is the likely process method to deposit RRAMs, Kirsch said, noting that “it is possible to stack planar layers on top of each other.” Moreover, if the uniformity of the RRAMs can be tightly controlled, it would be possible to create multi-bit-per-cell memories, much as NAND flash uses multiple levels of charge within each bit cell. A 4 bpc architecture is feasible, he said.

Dirk Wouters, an imec research manager, said conventional DRAMs are reaching scaling limits on several fronts. The aspect ratio of the capacitors is headed toward 50:1. Also, the high-k dielectrics used in the DRAM cell must be improved. Hafnium oxide may be replaced by zirconium oxide, with a k value of 40, and later with strontium titanate (SrTiO) and BaSrTiO. “Nature is not helping us, because the high-k materials have a lower bandgap, resulting in higher leakage,” Wouters said.

The track record of floating-gate NAND flash scaling has been impressive, with density doubling every year. But Wouters said at the 20 nm node, only 100 electrons will represent a bit, leading memory companies to develop alternatives such as charge-trap memories, and memories that stack vertical transistors within the die. With these vertically stacked transistors, manufacturers could relax the lithographic dimensions to 50 nm, for example.

“RRAMs represent a major materials challenge,” Wouters said, adding, “Nickel oxide etching is a serious issue at this moment.” At imec, MOCVD tools have created 8 nm thick layers of the metal oxides, but atomic layer deposition can achieve 5 nm.

On the logic side, Wouters said the industry will shift to multi-gate transistors, supported by 3D solutions with TSVs. Channels based on germanium and III-V compounds are likely. Further out, companies may be able to incorporate carbon nanotubes, nanowires and graphene.

Two speakers looked at TSV-related challenges. Sesh Ramaswami, a strategy manager at the TSV program at Applied Materials, described the equipment and materials challenges represented by TSV-enabled chips, which he said are “in various stages of late development.”

The vias-middle approach creates the TSVs after the contacts, in a fab-based process. Later, the wafers are thinned and backside contacts are created. In the vias-last flow, TSVs are formed from the backside after the wafer is thinned. While many of the TSV process steps are extensions of etch, deposition, plating, CMP and metrology steps, TSV chips will require new learning. Temperatures must be held to relatively low values, and bonding, handling and transporting the thinned wafers represent hurdles the industry will need to overcome. “The adhesive bonding and debonding is new to the industry,” Ramaswami said, adding that “much work remains to be done on standards.”

Robert Geer, an interconnect researcher and professor at the College of Nanoscale Science and Engineering in Albany, N.Y., presented research on ways to use TSVs to meet the bandwidth needs of tomorrow’s ICs. For ICs that process video, or on-chip RF modules, the bandwidth demands are enormous. For memory access, bandwidth of 2 Tbps is sufficient, but logic-to-logic computation requires 5-6 Tbps, and RF signals need even higher rates.

“As nice as TSVs are, they are still copper, which has a frequency limit of about 1 GHz,” Geer said.  By surrounding a signal TSV with four other TSVs used as shields, designers could accomplish the on-chip equivalent of a coaxial cable, achieving much higher bandwidths. Designers must balance their need for higher bandwidth with the fact that TSVs require space. “Every time we are using a TSV, we are losing device area,” Geer said.

— David Lammers, SEMICON West Daily News

Looking ahead to the next generation of IC design, process flows and the increasing number of advanced materials they entail, we see a real need for semiconductor companies to rethink traditional approaches to research and development as efficiency becomes increasingly vital for continued viability. As chip geometries continue to shrink, so do the timetables for development when considering market share and competitive advantage. With end-user product iterations speeding up (we are already on iPhone 4, for example), a collective “need for speed” in development has arrived. This is clearly evident in what has been called the Materials Age.

During previous economic downturns, it was common for manufacturers to examine tools closely with an eye toward increasing their efficiency. Even relatively small incremental gains could result in proportionally larger increases in throughput and yield. Today, companies are adding a new wrinkle by also seeking ways to boost efficiency at the molecular level. The application of high-productivity development methods are taking center stage as they significantly compress the time required to achieve fab readiness for newly introduced materials and processes, the result being that leading manufacturers can now add new weapons to their strategic arsenals in the form of innovations around materials and processes, and turn time into an ally rather than a foe.

Not so long ago, very few materials were in play in the semiconductor industry. Until the arrival of copper, a select group of dopants, dielectrics and a few other materials were heavily used with no or little ongoing modifications. Today, new nodes are requiring a dozen or more new materials, and this number is set to expand as more exotic materials are considered for viability. Companies are looking for competitive edges in high-productivity development techniques for identifying and integrating new materials faster. As faster, more productive approaches continue to emerge, we shall witness the passing of traditional R&D practices.

New methods, however, must solve the time-honored (and time-leaching) traditional approaches of sequential research process steps. These steps can typically take a year or two. Today, using high-productivity development methods — including combinatorial screening — many experiments can be conducted at the same time. While massive parallel processing has its advantages in time and cost savings, reaching the goals of speed to solution and maximized efficiency requires more than a capable partner and productive platform. It requires another element, namely collaboration.

Semiconductor companies are realizing what it takes today to deliver on the promise of new R&D techniques to solve materials challenges faster. With new process changes comes the engagement change. While willing to look more and more to outside guidance and new approaches to gain efficiencies, IC manufacturers must also be more willing to share information and collaborate with partners. In addition to newly applied technologies and techniques, this is a key contributor to realizing success in performance and efficiency gains in new material solutions.

High-productivity methods are already improving R&D efficiency and effectiveness while opening the door to significant economic gains. Manufacturers leveraging this approach are experiencing rapid learning cycles with minimum expenditures on silicon and test materials. With formulated chemistries and/or precursors, these high-productivity methods have been used successfully in applications such as copper-loop integration, advanced transistor materials and process flows, and advanced patterning.

The Materials Age combined with the recent economic downturn have helped to spawn a new age, where the needs for speed-to-solution and collaboration are key. It is the Age of Development Efficiency.

— Tod Higinbotham, Executive Vice President and General Manager, Microelectronics, ATMI Inc.

The semiconductor industry has become accustomed to the unrelenting march of progress led by Moore’s Law and the International Technology Roadmap for Semiconductors (ITRS), and takes somewhat for granted the miracle of two- or three-year rates of technology introductions. But in reality, technologies are rolled out over what takes typically at least 10 years. So if a manufacturer wants to be in the game, they need to be paying attention and going after prospective technologies very early.

Paolo Gargini, Intel Fellow and ITRS chairmanPaolo Gargini, Intel Fellow, director of technology strategy at Intel Corp., and chairman of the ITRS, detailed this point with example after example of similarly paced technology developments, and urged audience members to be thinking now for technology introductions beyond 2020. Gargini gave a keynote speech yesterday titled, “Welcome to the Next Decade!”

The CMOS process is undergoing a complete renovation that will further differentiate those companies that have developed an efficient means to bridge from risk research to high-volume manufacturing, according to Gargini. Much of what has transpired over the past couple decades has been predicted, including the end of classical scaling. But equivalent scaling techniques were long ago in the pipeline, so the transition from classical to equivalent kept progress on track.

For example, research initiated on strained silicon in the early 1990s went into manufacturing in the early 2000s, and research on high-k/metal gates in the mid-1990s went into manufacturing shortly after the mid-2000s. “I am confident that among the many possible solutions already demonstrated in research, we will continue to extract and introduce into manufacturing the next elements of equivalent scaling in a timely fashion,” Gargini said in a separate interview.

To that end, fundamental research has substantially increased. But it is no longer the domain of corporations, as it has shifted instead to universities, consortia, institutes and national labs. For any given research case, companies are able to select the most qualified universities on a particular subject, immediately access the expertise, and substantially reduce the time required to reach a fundamental understanding of subjects that may normally be outside the typical expertise of the corporation. At that point, consortia are useful to test the ideas in a pre-competitive environment. “Eventually, each partner company must do its own R&D work to adapt the best ideas to its product and manufacturing environment, and to differentiate its process technology for best competitive advantage,” Gargini added.

Intel, for one, has systematically applied a staged investment scenario to align the risks with the resources. It begins with external research at universities, for example; continues with research, evaluating a few options; pathfinding; development; and finally manufacturing.

According to Gargini, new device studies and process evaluations generated by the new approach have reached “unprecedented levels,” and have produced a new set of researchers from fundamental physicists to chemists and material scientists.

Some of the most innovative solutions that MOS technology has seen over the years include SiGe PMOS strained silicon, which made its debut in 2003. “This technology dramatically increased p-channel mobility, hence making it more efficient,” he said. In 2007, the introduction of high-k/metal gate (HKMG) reduced leakage by more than 100×, he added. “HKMG is the most fundamental change to the basic MOS transistor that the industry has seen in over four decades.”

Gargini gave special credit to George Scalise, president of the Semiconductor Industry Association (SIA) with keeping the semiconductor industry moving forward on the right roadmap because of his push behind the ITRS. And he credited the ITRS and its predecessor NTRS with predicting several significant developments that would enter manufacturing years later. The ITRS, for example, predicted in the 1990s that major innovations were going to be necessary to maintain device scaling at historical trends in the 21st century. A 1994 roadmap table also indicated EUV lithography as a key option for the evolution of lithography. “My opinion was that around 2010 would see something decent,” Gargini said.

Looking beyond 2020, Gargini said that Intel plans to keep all the CMOS logic benefits it has accumulated, but look at other new technologies such as spin transistors, quantum dots, carbon nanotubes, graphene and more. “Science doesn’t come with an instruction manual,” he said. “We’re doing all these experiments; who knows what we’re going to find out?”

— Aaron Hand, SEMICON West Daily News

Jordan Valley Semiconductors (Migdal Ha’Emek, Israel) and Nikon Precision Inc. (Tokyo) are the winners of the prestigious “SEMICON Best of West” award. These awards, presented Wednesday at the SEMICON West 2010 exhibition, are given based on the products’ financial impact on the industry, engineering or scientific achievement, and/or societal impact.

“Our judging panel was impressed with the products from this year’s finalists,” said Tom Morrow, vice president, global exhibitions and marketing of SEMI. “All of these products are worthy of recognition by the industry, and we had to make a very difficult choice. It’s also a testament to the breadth of the industry that we had finalists from around the globe showing such technical innovation.”

Jordan Valley’s winning product is the JVX7200 SiGe Metrology Tool, which, according to the company, combines advanced high-resolution X-ray diffraction (HRXRD) and X-ray reflectivity (XRR) channels to provide composition, thickness, strain, relaxation characterization and metrology for epitaxial layers such as SiGe and SiC, which are required for strained silicon processes. Additionally, the XRR channel can provide valuable information on other thin films, such as those found in high-k gate stacks. The tool is capable of providing rapid, in-line measurements and analysis on both blanket and product wafers.

Isaac Mazor, CEO, Jordan Valley Semiconductors Ltd.“Long ago, we had the vision to see the importance of the strained silicon process,” said Isaac Mazor, Jordan Valley’s CEO. “Our engineers were able to bridge the metrology gap for this process by building the most advanced platform for the most advanced technology available today. We thank the judging panel for this award, and we honor all the finalists for their achievements.”

Nikon Precision’s award-winning product is the NSR-S620D Ultra-High Productivity Immersion Scanner. According to Nikon, this tool incorporates the Streamlign platform and a 1.35 numerical aperture (NA) lens to satisfy the aggressive demands of double-patterned lithography at 32 nm, with extendibility to 22 nm applications. The S620D targets 200 wph, maximizes yield with 2 nm overlay and superior critical dimension uniformity (CDU), and enables rapid installation.

Stephen P. Renwick, principal engineer, Nikon Precision Inc.“It’s great to be recognized by this distinguished panel of judges for our tool,” said Stephen P. Renwick, principal engineer with Nikon Precision. “We think this is the right product for our customers, and we’re looking forward to great success. We think our engineers did an outstanding job, and they deserve a lot of credit.”

Before the 2010 award presentation, Jacob Mor, president and co-founder of Nano Green Technology, said, “Receiving this award in 2009 changed our company’s life. We immediately gained respect from the industry, and this award contributed to our success. We mentioned this award in sales meetings, in our product literature, and on our website, and we received orders for 70 of our units within the year.”

The selection of finalists was made by a prestigious panel of judges representing a broad spectrum of the microelectronics industry, academia and media. The judges were William Chen, senior technical advisor, ASE Group; Dao Giang, manager, external opportunities, Intel; Octavio Martínez, senior director, engineering, CDMA technologies, Qualcomm Inc.; Godfrey Mungal, dean, school of engineering, Santa Clara University; Mark Osborne, editor-in-chief, Semiconductor Fabtech; David Ridsdale, editor-in-chief, EuroAsia Semiconductor; and Pete Singer, editor-in-chief, Solid State Technology/SmallTimes.

— Steven Buehler, Global Communications, SEMI

We live in an increasingly connected world, combining computers, communications and consumers through technologies that are beginning to merge our virtual worlds with our real worlds. Ubiquitous connectivity, video with ultimate graphics, and 3D imaging are all key drivers for technology development. They’re penetrating the market very rapidly, and serve to illustrate the seemingly insatiable appetite of consumers for the advanced semiconductor devices behind the technologies.

Luc Van den hove, imec president and CEOLuc Van den hove, president and CEO of Belgian research center imec, described the networking, gaming and increasingly healthcare-related consumer technologies yesterday morning as a means to show the ever-accelerating need for data handling and computing power, and the relentless march of semiconductor scaling. Van den hove was the keynoter at this year’s Sokudo Lithography Breakfast Forum, where he put all this technology development into a perspective around lithography advances and continuing challenges.

For nearly 40 years, lithography was the only enabler of continued traditional scaling, Van den hove said, pointing out that this phase ended at the beginning of this decade when materials innovation (strained silicon, SiGe stressors, high-k/metal gates, etc.) took over at least part of the responsibility. For the next technology nodes, structural innovations such as finFETs will also be introduced, and could take the technology to 15 nm. And beyond 15 nm could see extreme high-mobility channel materials, for example.

Another technology innovation that is now beginning to take over from lithography’s traditional scaling is 3D integration, which brings vertical scaling into the equation and will help to increase performance considerably, Van den hove said.

Ultimately, however, the point is that what used to be a lithography-dominated world is now driven by what Van den hove referred to as concurrent scaling — enabled by lithography, materials innovation, and 3D stacking.

Evolution vs. revolution

Lithography continues to innovate and advance. When Van den hove last gave a keynote speech at the Lithography Breakfast Forum in 2006, he focused on the 32 nm node, posing the question: evolution or revolution? To be sure, the lithography technologies being used in production today have largely come about from an evolutionary perspective. Examples of that include computational lithography such as source mask optimization (SMO), used to enlarge the process window and squeeze as much out of existing 193 nm equipment as possible; and double patterning, which is also able to extend 193 nm immersion through a variety of schemes.

But Van den hove urged that the industry really needs to put in place EUV lithography, which is the most likely technology to carry the lithography forward, he said. One could argue that EUV is an evolutionary change as well, as an extension of optical lithography at lower wavelengths, but it’s a pretty massive departure from today’s excimer lasers and transmissive optics operating in atmosphere.

The beauty of EUV is its tremendous resolution power, Van den hove commented, and its higher k factors, which make life for the lithographers much easier. “Of course, fully reflective optics is creating quite a lot of problems,” he said, adding that the last issues related to the source “are being tackled at this moment.”

Imec, working on one of two existing EUV alpha demo tools from ASML, has been able to put a lot of work into EUV discovery, and seems to have become increasingly confident about its capabilities over the years. “We’ve exposed many wafers, and this is what is needed to mature the technology and solve problems to bring EUV into manufacturing,” Van den hove said. Imec has seen significant improvements in resist materials during last year, he also noted, adding, “We’re now getting resists that are getting very close to the targets in terms of sensitivity and line width roughness.”

Imec is one of six organizations that is slated to receive one of ASML’s pre-production EUV tools, the NXE:3100. The tools will begin shipping before year end. ASML very recently achieved first light with the first system — the Cymer source integrated and operating. Also speaking at the Lithography Breakfast Forum, Hans Meiling, ASML’s director product management EUV, gave an update on the integration status of the 3100. As of this month, ASML has completed the integration of three of the systems — one being used for investigating the status of throughput and overlay; another for imaging; and the third for a combination of imaging and overlay, Meiling said. Three more systems are in various stages of build-up.

Although the first EUV exposures have been made with one tool, the Cymer source is not yet up to full power. Two power upgrades are planned before the first lithography tool will be shipped to a customer. The first upgrade, Meiling explained, will increase CO₂ laser power by increasing the laser gain length. The second upgrade will increase CO₂-to-EUV conversion efficiency.

Maskless lithography

Meanwhile, imec’s Van den hove also talked about the prospects of maskless e-beam lithography, and where it might fit into next-generation lithography development. “EUV is the most likely technology, especially for high-volume activities, but I don’t mean to say there is no room for alternatives,” he said.

However, challenges in e-beam lithography for mainstream semiconductor manufacturing are also tremendous — comparable to EUV, but without the resources that EUV has had devoted to it. Imec considers multi-beam e-beam development to be understaffed, Van den hove said, making it difficult to overcome technical hurdles. He suggested (as was discussed at a recent Sematech event) that the industry should focus on developing the multi-beam technology for mask writer, “and see if the technology makes sense. Then we could develop it for wafer writing.”

Mapper Lithography seems to have different ideas, though, and continues to focus on the wafer writing business. Bert Jan Kampherbeek, vice president of market development and co-founder, said the Dutch company’s objective is to provide a solution for 32 nm half-pitch and beyond — for traditional contact and via layers at first, but also metal and other layers at 32 nm and beyond.

Although e-beam is known not only for its high resolution but also its slow throughput, Mapper’s roadmap takes the technology up to 10 wph. Although that’s still quite slow compared with other technologies, Kampherbeek conceded, the machines are small and cheap, so could be clustered extensively to bring throughput up to 100 wph or more.

But first Mapper needs to get its technology from the 110 parallel electron beams that are on its pre-alpha tool, to the planned 13,000 beams slated for high-volume production. “Actually, as you might think, especially from a data point, this is very challenging,” Kampherbeek said, noting that the total data rate needed is ~100 TB/s. “But we know we can do this with existing hardware.” Other technical challenges need to be overcome as well, including those related to electron optics, contamination and position stability.

— Aaron Hand, SEMICON West Daily News

As might be expected, this week’s SEMICON West is a much more upbeat affair than it was the past couple years, with the industry well into a recovery from one of the worst downturns in its history. During the first day of exhibits yesterday, booth traffic seemed lively in a way it hasn’t been recently. SEMI’s annual press briefing before the opening of the show reflected the prevailing mood.

Jonathan Davis, president, SEMI North America“This is really an exciting time as the industry begins a multi-year recovery,” said Jonathan Davis, president of SEMI North America, as he opened the presentations, adding later, “I kind of want to savor this moment. I don’t know how many more times I’m going to be able to stand up here and say that the market’s going to double this year.”

Davis was alluding to the latest predictions for semiconductor equipment sales, which are expected to rise from $15.92 billion in 2009 to $32.50 billion this year. Combined predictions from eight of the industry’s analysts show semiconductor revenue rising this year by 28.7%. That’s up considerably from what they were predicting at the start of the year, according to Stan Meyers, SEMI’s president and CEO. “The forecast from the same group in January was 14.9%,” he said. “So basically they doubled their view of the semiconductor industry in just six months.”

Gartner expects significant electronics growth this year, with PC unit production expected to rise 22% and cell phone unit production 14%. Samsung Electronics, the biggest television manufacturer in the world, recently raised its flan panel television sales targets from its earlier predicted 39 million units to 50 million units this year, according to Meyers. “This is all good news,” he said. “More demand, more products, more silicon, more materials and more equipment.”

It could be better, however. Although forecasts for semiconductor revenue have a nice trend upward, equipment spending as a percentage of that revenue is moving in the opposite direction, peaking at 24% in 2000 and hitting a low of 7% in 2009. “I’m very concerned at this point about the lower percentage of revenue investment in equipment,” Meyers said, adding, “I’m concerned that we may not be investing enough to maintain the innovative approaches.”

— Aaron Hand, SEMICON West Daily News

With a focus on the environment, SEMI yesterday announced the five finalists for the SEMICON West 2010 Sustainable Technologies Award. Featured at the Global Care luncheon event, discussions also turned to Sony Electronics’ efforts to achieve a zero environmental footprint by 2050.

Achieving sustainability is an important goal for leading companies today. The annual SEMI Sustainable Technologies Award recognizes the efforts of SEMICON West exhibitors that have developed and introduced equipment, materials or services into the marketplace in the past three years that contribute to sustainable improvement of the environment. The five finalists:

• Applied Materials Inc. for iSYS, a subfab system that synchronizes the operation of vacuum pumping and abatement technologies from 10 major suppliers with the wafer processing tool.
• Edwards Ltd. for eZenith, an integrated vacuum and abatement system resulting in up to 10% power reduction on vacuum pumps and 50% lower fuel for gas abatement.
• Pall Corp. for its Water Reclaim System, which enables water to be reclaimed from silicon processing operations, resulting in 90% of spent process water recovered.
• Tokyo Electron Ltd. (TEL) for Expedius+, an intermittent open and close technology for de-ionized water (DIW) flow valves, application for idling mode, and built-in scrubber.
• Verigy Ltd. for its V93000 Test Platform, which conforms to virtually all guidelines for low environmental impact.

SEMI’s Sanjay Baliga with representatives from two of the five finalists: Vivien Krygier, Pall; and Mike Czerniak, Edwards.A single award winner will be selected from these five finalists, with the award winner announced at the SEMICON West TechSITE South today at 11:30 a.m.

Reaching for no footprint

Sony announced in April that its global environmental goal was to achieve a zero environmental footprint throughout the lifecycle of its products and business activities. Called “The Road to ZERO,” Mark Small emphasized that Sony’s the goal is to achieve a zero footprint by 2050, with mid-range targets for 2015, according to Mark Small, Sony’s vice president of environment, safety and health.

This is a tall order, but Small believes that it’s possible by focusing on four environmental perspectives (conserving resources, controlling chemical substances, curbing climate change, and promoting biodiversity), and by addressing the entire product lifecycle (R&D, product design, procurement, operations, distribution, and “take back and recycling”).

Sony plans to meet its global 2015 goals by reducing the mass of its products by 10% (from 2008), reducing waste generation by 50% (from 2000), improving its waste recycling rate worldwide by 99%, reducing water consumption by 30% (from 2000), and reducing energy consumption of products by 30% (from 2008).

Sony is vigilant about what goes into products, and conducts audits to ensure that suppliers and vendors are also adhering to sustainability practices. The Green Partner program was implemented in 2003 and now has 3,700 companies worldwide. The program aims to ensure that parts used in Sony’s manufacturing process do not contain globally banned substances. The certification process for direct material suppliers involves supplier audits, signing of the Green Partner Agreement, and submission of various documents to meet Sony Technical Standard SS-00259. The Green Partner certification is valid for two years.

Sony’s recycling programs

“Sony Style” is a trade-in program for many brands of eligible products. The consumer receives an offer for the product’s trade-in value and gets a Sony Style gift card for the value of the trade in: laptops, cameras camcorders, MP3 players, game systems, and mobile phones.

Sony GreenFill e-Recycle Program is a retailer partnership program about easy recycling with all brands accepted for small items. In addition, Sony also focuses on consumer recycling responsibility. In September 2007, Sony launched a major consumer recycling program with drop-off locations nationwide. Any product that is Sony-branded is recycled at no charge. So far, nearly 30 million pounds of Sony products have been recycled.

Sustainability business

“Sustainability is the apple pie and motherhood of the 21st century, and for better or for worse, perception is reality,” Small said. No one is against sustainability, he added, so companies need to get involved and make it happen. However, he reminded the audience, “If it does not make economic sense, then it is not sustainable.”

Companies can make sustainability smart business. For more information on SEMI and sustainability, please contact Sanjay Baliga at [email protected].

— Deborah Geiger, SEMI Global Communications

Rick Wallace has been appointed chairman of the SEMI International Board of Directors for the 2010-2011 term, taking office today at the annual SEMI membership meeting during SEMICON West. What follows is his perspective on a global technological transformation.

Not that long ago, many of us wouldn’t have fathomed the technology that is now crucial to our everyday lives. As we enter the second decade of the 21st century, the world continues to undergo a technological transformation as significant as the Industrial Revolution.

Today’s technology is enabling a whole new frontier of productivity and connectivity — breaking down barriers both in the workplace and at home in a way we never thought possible. It’s allowed us to be more nimble and more responsive. It has brought us closer together across the globe. At a pace that’s evolving ever so rapidly, technology has changed us forever, and the end of the technological revolution is nowhere in sight.

In a competitive landscape dominated by form factors, app stores and operating systems, the glory days of the processor wars — when silicon innovation drove each wave of new technology — would appear to be ancient history. Nothing could be further from the truth. Semiconductor technology is very much at the heart of today’s revolution. Daily, we chart new territory in our collective quest to innovate and push the limits of Moore’s Law, enabling next-generation semiconductors that will power tomorrow’s life-changing technology.

I want to thank Stan Myers and the members of SEMI for the opportunity to be part of this organization at this critical time. I look forward to working with the SEMI Board and global membership to drive innovation, transition and change.

— Richard P. Wallace, President and CEO, KLA-Tencor