ASML announced today broad support for its holistic lithography products that the toolmaker introduced last year at SEMICON West — products designed to optimize litho scanner performance, widening the process window. ASML said that 100% of its leading-edge scanners (primarily the NXT:1950i model) are now sold with at least one holistic lithography component.

Coming about in large part because of ASML’s acquisition of Brion Technologies in early 2007, holistic lithography integrates computational lithography, wafer lithography and process control to optimize production tolerances for chipmakers. Customers have adopted multiple products from the portfolio — including source mask optimization (SMO), FlexRay, LithoTuner, Baseliner and YieldStar — into R&D and volume manufacturing.

Source mask optimization (SMO) is a key component of ASML’s holistic lithography approach.Also gaining momentum, particularly since the end of last year and this year, is ASML’s Eclipse, which is a customized integrated package of products and services geared toward specific customers, nodes and applications. “The idea there is to try shrink the very last bit of performance that we can out of a process by leveraging this scanner, and the capabilities we have developed over the past several years,” said Bernardo Kastrup, director of applications products for ASML.

STMicroelectronics is one example of a chipmaker that will incorporate Eclipse with its NXT:1950i scanner for the 28 nm node, focused on improving overlay and CD uniformity (CDU). ST’s package includes a full range of products, including scanner tuning products, immersion scanner application, stabilization and conditioning, and applications support. Preparations for Eclipse at the next node have started with a feasibility study on 20 nm critical layer printing options.

“To optimize development cycle times and manufacturing solutions for 28 nm and beyond, ST is working closely with ASML to define targets, processes and design parameters,” said Joel Hartmann, Technology R&D Group vice president and general manager advanced CMOS, derivatives and eNVM technology at STMicroelectronics in Crolles, France.

ASML’s holistic lithography approach is a direction the industry has taken to get the most out of existing tools, delaying the inevitability of double patterning and/or EUV lithography. It enables chipmakers to “really pull all of the tricks from the bag and continue to shrink,” Kastrup said.

— Aaron Hand, SEMICON West Daily News

In semiconductor manufacturing, innovation and operations must be tied to value. The tools that connect technology to value, operational models, mimic the operation (i.e., a factory, a business, a process), in whole or in part, to assess whether the path the organization is on (roadmaps, developments, etc.) will achieve the desired results. The concepts are tested in software to determine the payback, allowing smart choices to be made about the next steps for the business. At the core of operational modeling is one simple principle: Every decision, even a decision that appears technical, is a business decision.

The tools — cost of ownership (CoO), cost and resource modeling, and discrete-event simulation — have resulted in massive improvements in cost and performance. The underlying standards developed by SEMI for the semiconductor industry have also been ported over to the flat panel display (FPD) world and they also port over to the photovoltaics (PV) world. The methods that allow information to be analyzed are common to semiconductors, display, magnetic heads, crystal growing, solar cells, solar modules, and thin-film panels. These are solved problems.

Looking at common methods employed today, intuition does not work well when more than a few variables are in play. Most analyses are laden with subtleties. Single-product factories quickly become multi-product factories with embedded development lines. Companies are constantly ramping products up and down. One company might adopt cash flow as the most critical metric, another company might choose internal rate of return (IRR). Quick and dirty spreadsheets used for simplified “greenfield” situations have proven woefully inadequate in real-world situations.

Using a simple concept to illustrate the way forward, let’s look at changing a material at a specific process step. How does this change the cost? There are several possibilities. The material itself has a cost. The material may impact the tool it is used on in several ways, such as reliability, preventive maintenance, or throughput. It may impact other materials or waste disposal. It may impact multiple processes, not merely the one process where the material is used. Some of these impacts, such as a change in tool productivity, can change the factory physics. It may impact yield, the value of the finished unit, and even the probability of a failure in the field. One modest change can have a large number of impacts. In practice, while it is possible to model everything, most decisions require far less rigor.

When a potential change is identified, the next step is to determine the areas of impact. There is a tendency to limit the analysis to areas where it is easy to gather data, while avoiding what might be more challenging or time-consuming areas of data collection/analysis. This is where we find out if management is serious about optimizing the business, since several things become apparent rather quickly. Does management provide adequate time to do a proper analysis? Are the necessary resources, tools and/or experts available to do the analysis? Are data sets readily available that allow the analysis to be performed more efficiently?

The proper use of operational models involves determining the right set of items to consider, not merely what is easiest. This is done by using a list of questions to guide the user in setting up the analysis. In the previous example, one question is, “What other process steps might change based on the original change?”

Once the set of questions has been developed, the next step is to determine the appropriate analysis tool. To analyze a process step, where the issues are essentially self-contained within the step, CoO is a very effective tool. To look at sequences that are self-contained, a different form of CoO can be used. If the entire factory — or a significant portion of it — is impacted, then factory-level modeling tools are required.

SEMI and Wright Williams & Kelly Inc. (WWK) will present their annual “Understanding and Using Cost of Ownership” course Thursday starting at 9 a.m. at the San Francisco Marriott Marquis. The one-day workshop will provide semiconductor and solar industry attendees with an expert understanding of CoO and overall equipment efficiency (OEE). From fundamentals and industry standards (E10, E35, E79), to applications and misuses, attendees will gain practical knowledge they can immediately employ. Use the latest generation of software developed for Sematech to examine your own equipment, materials and factory conditions.

To sign up for the workshop, visit the SEMI booth just outside the entrance to Moscone North.

— David Jimenez, President, Wright Williams & Kelly Inc.

Advanced packaging plays a critical role as semiconductor technology continues to fuel growth of new applications in consumer, healthcare, home, automotive, environmental and security markets. Packaging technologies help deliver the increased performance, low power, lower cost and smaller form factors that these applications require, and wafer chip-scale packaging (WCSP) has enjoyed significant growth over the past few years as a result of attributes to this end.

WCSP delivers reduced package footprints, lower costs, improved electrical performance and a simpler construction over conventional packages. An additional advantage is that the technology does not typically require underfill to meet board-level reliability requirements, and the implementation of enhanced co-design strategies should maintain this benefit into the near future.

As WCSP evolves, the integration of TSV interconnect technology will be required, enabling the stacking of ICs or other components to create highly integrated systems. TSV is an ideal solution for applications requiring higher performance, lower power and smaller form factors.

There are various configurations to stacked package assembly through TSV, and each has its advantages. The “via last” process (vias formed prior to wafer thinning within BEOL levels) is the most cost-effective solution as the TSV and back-side RDL are fabricated simultaneously. The “via middle” process (vias formed after completing WCSP wafer processing) is ideal for situations requiring fine-pitch and smaller via diameters, as those features address performance requirements and enable die size entitlement. Alternatively, final packaging could be standalone TSV-WCSP only, where components would be stacked similar to a package-on-package or embedded in a substrate or PCB laminate.

There are several development areas toward enabling stacked WCSP. These areas include TSV etch and plating steps, component stacking interconnect and assembly, and overmold material selection to minimize wafer- and package-level warpage. In addition, there are efforts underway to select wafer bonding adhesive and address the handling and shipping of thin (molded or unmolded) wafers or dies.

The transition to integrate TSV brings several reliability and manufacturabilty challenges. For instance, the addition of underfills and mold compound materials may change package moisture sensitivity levels. Managing warpage at the wafer level and final package level will become crucial to avoid SMT issues. In addition, TSV dies will be more prone to die cracking or dielectric and delamination issues. Collaborative efforts across the industry are underway today to address these issues.

WCSP is a mainstream packaging technology addressing customer requirements for lower costs and faster time to market, and demand for the technology continues to grow. As we move into the future, 3D structures will deliver increasing performance, smaller form factors and lower costs in semiconductor products.

— Dave Stepniak, Wafer-Level Packaging Manager, Texas Instruments

Based upon the experiences of other industries, technology developments in solar cell efficiency and increases in manufacturing economies of scale will not be enough for photovoltaics to reach grid parity goals as fast as the world desires. The solar PV industry needs to look at meaningful cost reduction through a global, robust and well-organized supply chain.

The current learning curve for the industry is not as steep as other electronic industries, especially semiconductors, which use many of the same processes, materials and suppliers as PV. A faster learning curve for the PV industry could be accomplished through better industry collaboration, including industry standards and technology roadmaps.

The progress made by semiconductors in cost reduction is one of the technological marvels of our time. Since 1975, the cost of one transistor has been reduced by a factor of ~4 million. This achievement has often been ascribed to Moore’s Law, the prediction that the number of transistors that can be placed inexpensively on an IC would double approximately every two years. Learning curve cost reductions summarized by Moore’s Law have led to the dramatic market expansion of chips into nearly every facet of modern life, and many observers see it as a useful guide to cost reduction in the PV industry.

Although thin-film and crystalline silicon (c-Si) cells do not benefit from lithography-enabled feature-size reductions that comprise many of the cost reductions in semiconductors, much of Moore’s Law is directly related to productivity, yield and other cost reductions not related to feature-size reductions. Since PV manufacturing is based on many of the same processes and materials as IC and display manufacturing, there remain important lessons from these industries that can be applied to solar cells and modules.

For more than 20 years, keeping pace with Moore’s Law was accomplished by individual companies, working independently on common technical problems. For decades, the idea that a technology roadmap for semiconductors was necessary to sustain an acceptable rate of industry progress was simply not part of anyone’s expectation. It was not until the 1980s that the first international roadmap for technology development was produced. Today, the International Technology Roadmap for Semiconductors (ITRS) is recognized as a natural and necessary compass and integral component of the IC industry.

Many see the ITRS process as an effective way to identify and target key requirements. Some also believe that the PV industry could benefit from the experience of the ITRS. There are both similarities and differences between the critical roadmap issues in chips and PV. Both involve substrates, interconnects, absorber/efficiency, metrology, packaging and test. Both have common business drivers such as cost reduction, throughput, quality and reliability, and sustainability. PV is clearly different from chips, however, and does not have the powerful organizing paradigm of the next process node that helps ground the semiconductor roadmap.

Industry standards also have a close relationship to technology roadmaps. It has been said that roadmaps without standards don’t work. Roadmaps are the group view of the technology path over time. Standards are the tools the industry uses to identify the set of specifications that define industry requirements. Several studies have identified billions of dollars in industry costs that the semiconductor industry has eliminated with standards. Are there similar costs in the PV industry that can be reduced with a smart standards effort, getting PV closer to grid parity? Many believe there are.

The PV industry is just starting to address roadmaps and standards. Several manufacturing standards have already been adopted by the industry, and there is a growing participation by key constituents in the standards development process. Active PV standards committees are in place in North America, Europe, Japan and Taiwan under the SEMI International Standards Program, the same platform and process that supports IC manufacturing standards.

One major standard specified how different machines or processes communicate together, a fundamental requirement for the modern automated factory and huge contributor to manufacturing efficiency. The standards effort in PV appears to be well on its way to contributing to a steeper learning curve.

Roadmaps are just now being considered by the industry. A recent survey of cell and module manufacturers, equipment and material suppliers, and other key players ranked lack of an industry roadmap and effective collaboration second behind government polices as a key barrier to industry growth. However, some industry participants believe it is too early for a technology roadmap and that engaging in an open, public dialog could be harmful. Collaboration opponents object that roadmaps cannot define industry growth in such a dynamic market environment.

Technology roadmaps and industry standards are complex issues for the industry to consider, involving fundamental issues of competition and cooperation. Along with the recently formed European Crystalline Cell Technology and Manufacturing Group (CTM), discussions are underway between other key stakeholders around the world trying to identify areas where cooperation makes sense. As these discussions continue, the industry has the opportunity to learn from the semiconductor industry and find its own path, to find its own Moore’s Law that drives down costs and accelerates grid parity, enabling a great solar era unsupported by government incentives.

SEMI’s PV Group has organized a PV Industry Collaboration Workshop taking place today at 2-6 p.m. at the Intercontinental Hotel, as part of Intersolar North America. The workshop features presentations from several key industry participants, break-out sessions, and conclusions and consensus on priorities moving forward.

— Bettina Weiss, Senior Director, SEMI PV Group

Three new innovative demonstrators — 15 µm wide SiGe micromirrors, grating light valves and SiGe accelerometers — have been built in imec’s SiGeMEMS technology platform. With this CMORE technology platform, imec offers a generic CMOS-compatible MEMS process for the monolithic integration of MEMS devices directly on top of CMOS metallization.

The demonstrators were built in the frame of a Flemish Strategic Basic Research (SBO) project called Gemini by imec and its project partners, Ghent University (UGent) and Katholieke Universiteit Leuven (K.U. Leuven). They illustrate the broad applicability of the technology platform.

Imec’s SiGeMEMS technology is based on a MEMS-last approach, where the MEMS are processed after and on top of the CMOS circuits (Fig. 1). It enables monolithic integration of CMOS and MEMS, integrating MEMS devices with the driving and readout electronics on the same die. This leads to a better performance compared with other integration schemes — with a better signal-to-noise ratio through a reduced interconnect parasitic resistance and capacitance, a smaller die size and package, and lower power consumption.

1. This graphic illustrates a schematic cross-section of a MEMS device created with imec’s baseline SiGeMEMS platform.The SiGeMEMS platform is versatile. It consists of standard and optional modules that can be processed at ~450ºC above standard CMOS, with many possibilities to tune and optimize the modules. The standard modules provide, for example, a CMOS protection layer, MEMS via and poly-SiGe electrode, an anchor and poly-SiGe structural layer, and thin-film poly-SiGe packaging. Optional modules, such as optical, piezoresistive or probes, can be added depending on the application.

The platform’s flexible and modular approach allows application-specific tuning and optimization. An example is the thickness of the MEMS structural layer, which can vary between 300 nm and 4 µm. A 300 nm thick layer allows the manufacture of optical MEMS, such as the micromirrors and gratings discussed here.

For such devices, the process is extended to add various coatings with specific reflective properties. A 4 µm structural layer is used, for example, to create inertial sensors or actuators such as the Gemini accelerometer (Fig. 2). Other possible applications of the technology are µmicrophones, µspeakers, µsensors, probe-based memories and micropower generation.

2. An in-plane (left) and out-of-plane (right) SiGe accelerometer.The Gemini mirror design uses an innovative actuation mechanism, relying on six electrodes (using two possible electrode thicknesses of the SiGeMEMS platform). Two of the six electrodes serve as landing electrodes. The other four attracting electrodes are driven by two anti-phase saw tooth signals and two fixed analog voltage signals. By applying this signal scheme, the duty cycle of the mirror is modulated in an analog way.

Laser Doppler vibrometer measurements have confirmed the feasibility of analog pulse width modulation (PWM) for 15 µm wide SiGe micromirrors, which have been designed for use in a display system. The novel actuation mechanism enables the display of a large range of grayscale values. The six-electrode design combines the advantages of analog driving (no contouring effects) with that of a full-swing mirror movement (simpler optical system and higher response speeds).

A grating light valve is a MEMS reflection grating that produces bright and dark pixels in a display system, by controlled diffraction of incident light due to electrostatic deflection of microbeams. In the Gemini grating light valves, the microbeams are clamped beams suspended over an electrode, which can modulate the intensity of the diffracted light when an actuation voltage is applied to half of the beams. Display systems consisting of such a technology provide a high contrast ratio, high resolution and high brightness. Both the mirrors and grating light valves are realized with a 300 nm thick SiGe structural layer.

For the Gemini accelerometer, both in-plane and out-of-plane low-g designs have been proposed. Measurements of a fabricated out-of-plane accelerometer show that this device can sense the gravitation projection to the main sensing axis with an average sensitivity of 0.5 mV/g. This sensitivity is comparable to the state-of-the-art, but above-CMOS integration will greatly improve the state-of-the-art noise performance of such accelerometers. The accelerometers have been built with a 4 µm thick SiGe structural layer to obtain an improved capacitive readout of the in-plane devices.

Imec CMORE SiGeMEMS services include feasibility studies, design and technology development, prototyping and low-volume manufacturing. In addition to these services, imec recently announced a new SiGeMEMS foundry service. This service is based on the SiGeMEMS platform, fixing the options in a baseline process with a 4 µm SiGe mechanical layer. It is supported by mature design kits for the most important commercial MEMS design tools, and allows interested parties to develop their own MEMS designs for rapid prototyping.

In addition, for universities and research centers, there is a multi-project wafer (MPW) service. By gathering the designs of multiple customers on the same mask set, MPWs enable the fabrication of test structures and prototypes of devices at low cost. A first MPW run, scheduled for the end of 2010, will be processed on a wafer with a single metal layer, and is meant for initial prototyping. A second run, with full capability and with the SiGeMEMS devices on top of TSMC 0.18 µm CMOS, is scheduled for mid-2011.

Imec’s SiGeMEMS services are part of its CMORE offering. With CMORE, imec offers companies all the services needed to convert their ideas into smart packaged microsystem products. The CMORE toolbox contains a wide variety of device technologies (including high-voltage technologies, CMOS imagers, photonics or MEMS) and packaging capabilities (such as through-silicon vias and MEMS capping), as well as design expertise and testing and reliability know-how. Through its partners, imec can also offer a path to transfer the technology to the foundry for volume production.

— Ann Witvrouw, Mieke Van Bavel, and Jan Provoost, imec

With the potential to address the rising demand for smaller, more functional, and lower-power chips, 3D architecture is emerging as a prime candidate for meeting leading-edge chip requirements. Through-silicon vias (TSVs) appear to be a viable solution. Indeed, industry interest in emerging 3D TSV technology has grown, given its adaptability to both die-to-die and wafer-to-wafer stacking. The TSV approach merges the performance and functionality of system-on-chip (SoC) architecture with the functionality, cost and time-to-market advantages of system-in-package (SiP).

Among the key processing steps that enable 3D integration are alignment and bonding, which allow for the interlayer connection of TSVs that provide the electrical interconnects. Wafer-to-wafer (WtW) and die-to-wafer (DtW) bonding is key to the 3D interconnection of wafers by stacking. Precise alignment is one of the major challenges affecting the performance of 3D interconnects.

The first metrology challenge starts when the wafers are bonded. In wafer-to-wafer bonding, pre-bond inspection is critical to ensure the proper interconnect alignment. If the bonded wafer pair is misaligned or if the overlay is insufficient, the bonding quality can be compromised. Therefore, it is important to analyze all the contributing factors to the alignment accuracy.

IR microscopy can be used to measure the overlay accuracy of the bonded wafer pairs required for 3D interconnects.Infrared (IR) microscopy is a non-destructive, in-line metrology technique that can be used to measure the overlay accuracy of the bonded wafer pairs required for 3D interconnects. It is a method capable of “seeing” through the silicon, which enables a variety of metrology techniques, including the calculation of overlay error. IR can measure the overlay error in bonded wafer pairs immediately after the pair leaves the bonder. As a result, overlay can be quantified and compared to design overlay tolerances, and decisions can be made on whether to continue the processing steps to complete the 3D integration.

However, measuring opaque films and the high-aspect-ratio features that dominate 3D architectures still poses some challenges. Metrology for 3D architectures requires new techniques, revisiting and improving some older techniques, and breakthrough innovations to create new metrology tools.

To gain a better understanding of how new and existing wafer metrology technologies can be used, modified or enhanced to measure and improve 3D interconnect processes, Sematech is hosting a 3D Metrology Workshop on Wednesday at 1 p.m. at the Marriott Marquis, in conjunction with SEMICON West.

To identify critical issues and gaps, technology timing, and key process specifications, a collaborative, industry-wide approach must be adopted to develop and implement solutions for making critical, next-generation interconnects manufacturable. Sematech’s 3D Interconnect program has made a case for TSV’s commercial viability, and has been investigating the integration of both die-to-wafer and wafer-to-wafer 3D technologies, including process development, TSV reactive ion etch, wafer bonding, wafer thinning, die bonding, TSV metallization, and accompanying metrology techniques.

— Sitaram Arkalgud, Director of 3D Interconnect, Sematech

As consumer demands continue to drive increased chip performance, the semiconductor industry is abuzz with the possibilities of 3D IC integration. Qualcomm Inc., looking from the point of view of a mobile wireless company, sees significant potential in 3D IC architectures, developing some exciting new applications that are perfectly suited to the benefits of high-density chip stacking.

Matt Nowak, senior director of advanced technology, QualcommAt the opening keynote yesterday morning for the Advanced Semiconductor Manufacturing Conference (ASMC), held at the Marriott Marquis in conjunction with SEMICON West, Matt Nowak, senior director of advanced technology for Qualcomm, showed audience members increased smart phone functionality in the form of “augmented reality.” This technology that Qualcomm is working on uses a smart phone to take a picture of a scene, which the user can then click on to get more information about local restaurants, entertainment and more.

Citing a market forecast from Yole Développement, with 3D integration becoming a multibillion-dollar wafer market by 2013, Nowak said that smart phones and smart books represent one of the fastest growing application segments for 3D. “These devices are always on and always connected, and location-aware at all times.” Augmented reality is a “very interesting application for high-density through-silicon stacking,” Nowak added, noting its need for very high bandwidth and functionality in a very small form factor.

3D integration comes in any number of sizes and flavors, each with its own set of challenges and opportunities. Monolithic integration is still in the research phase, but there are various forms of stacked ICs that are currently in production. Package on package (PoP) and package in package (PiP) are being produced in high volumes, as is bare die stacking without through-silicon vias (TSVs), Nowak said.

Bare chips with TSVs are not yet in volume production, but show considerable potential. High-density through-silicon stacking (TSS) was the focus of Nowak’s keynote discussion. The technology uses small-diameter (~ 5 µm), high-aspect-ratio (~10:1) TSVs; a via-middle process flow, with the TSV being formed after FEOL; backside wafer interconnect processing; high-density tier-to-tier microbump connections; thousands of TSVs and microbumps per chip; and includes design and test enablement, tools, and methodologies.

Probably the biggest motivation for the technology is that it enables architectural innovation, Nowak said. “If you can do it with wire bond, you probably should because it’s going to be cheaper,” he said. “But this technology can be very differentiating.”

Over the past year or so, high-density through-silicon stacking has gathered a lot of momentum, and particular work has gone into design strategies and methodologies, Nowak said. But of course the technology is not without its challenges. There’s no consensus for standard manufacturing flows, yield and reliability are not proven, there’s a lack of consensus with regard to cost targets, and the industry is yet to decide who will do what in the supply chain, he said. The ecosystem needs to be established; and process flows, roadmaps and fundamental standards need to be put in place. “We need to figure out where we’re going.”

Packaging expert Phil Garrou, in an October blog for Semiconductor International, likened the challenges facing 3D integration to the Four Horsemen of the Apocalypse, identifying them as manufacturing cost, test, thermal management and design. “We’re well on the way to taming these beasts,” Nowak said.

There are several cost contributors for manufacturing, including the silicon area for TSVs (you can’t put circuits where you put the vias), incremental test cost, TSV and microbump yield loss, and incremental TSS process steps. But there are also several opportunities for cost savings, Nowak said, pointing to variability in the laminate package size and number of layers, and the ability to split a very large die into two higher-yielding die, split a die into heterogeneous technology nodes, and aggregate metal layers to reduce the total number. All of these are very dependent on the application, however, he added.

For the TSS high-volume manufacturing process, cost is very dependent on materials, which make up 44% of the cost in one example Nowak showed. So significant cost savings could be introduced through material innovations. Equipment cost-of-ownership (CoO) improvements could figure prominently as well, since equipment depreciation accounted for 27% of the cost.

The next important step for TSS, Nowak said, is to start putting standards in place for the technology, including standards for EDA tool data formats, design for test (DFT), stackable die interfaces, metallurgies, shipping carriers/transport of thinned wafers, temporary carriers and handling of thin wafers, ESD protection, reliability criteria, quality assurance specifications, and non-destructive metrology. “The through-silicon stacking ecosystem and standards need development,” he said.

SEMI and Sematech are partnering on a workshop today at 1 p.m. at the Mariott Marquis, titled, “3D Interconnect Challenges and Need for Standards,” moderated by Urmi Ray, a senior member of the technical staff at Qualcomm.

— Aaron Hand, SEMICON West Daily News

Although Germany has traditionally dominated the photovoltaics end-use market, PV industry players see tremendous growth potential in the United States, where the utility market is considered particularly attractive. “The U.S. market is poised for substantial growth that’s expected to be the largest in the world,” commented Gordon Brinser, vice president of operations at SolarWorld Industries Americas Inc.

Gordon Brinser, vice president of operations, SolarWorld Industries AmericasSolarWorld, whose global headquarters are in Bonn, Germany, is one PV device manufacturer that has brought at least some of its production to the United States over the past several years. In late 2008, SolarWorld opened North America’s largest solar cell manufacturing facility, a 500 MW facility in Hillsboro, Ore.

Brinser spoke during yesterday’s North American PV Fab Managers Forum at Intersolar about the impetus behind expanding into the North American market. SolarWorld’s decision to locate in the United States was dependant on several factors, he said, including proximity to key markets, state and local incentives, a fast ramp to 500 MW, and a skilled workforce.

Manufacturing in close proximity to key markets is a significant factor, Brinser said, noting the ability to work directly with end customers to enable quick and correct solutions, faster improvement cycle times to market and feedback from customers, and lower inventory costs.

The lower shipping costs that come about from closer proximity to end markets is not inconsequential because of the considerable weight of the solar panels, noted Julie Blunden, executive vice president, public policy and corporate communications for SunPower.

Julie Blunden, executive vice president, public policy and corporate communications, SunPowerBlunden also spoke at the PV Fab Managers Forum, but from a different perspective, given that SunPower is a California-based company that has traditionally done its manufacturing in Asia. SunPower has encountered substantial shipping costs from Asia, she said, and also a substantial hit in time as panels spend weeks being shipped across the ocean. So it was a meaningful decision to start building solar panels in the United States.

SunPower has committed to doing exactly that, with plans to begin production by this fall in Milpitas, Calif., just down the road from its San Jose-based headquarters. SunPower is partnering with Flextronics Inc. to produce 75 MW of solar panels annually at Flextronics’ facility.

It was not a decision made lightly. Although the United States is indeed an attractive market, and California in particular shows the most promise within the country, the cost of manufacturing in the United States is significantly more expensive that it is in most Asian countries. Cost challenges come in the form of capital, labor, utilities and taxes, Blunden noted.

But besides costs, market certainty is another important component of the location decision, with factors including volume and growth rate, disruption, and substitute prices, Blunden said. “We select first for cost, and second for market certainty,” she added, noting that when SunPower began manufacturing in the Philippines, the company knew it wouldn’t be a meaningful end market, but the location gave access to low costs.

What tilted SunPower toward California was long-term market demand, Blunden said, noting that they could’ve had lower costs in another state, but not with the confidence of market demand right out of the gate.

Cost challenges in the United States have been addressed through a variety of measures, including lower working capital, lower transportation costs, shipping benefits, new tax incentives, utilities, and considerations in capital and labor costs. Blunden pointed to the U.S. Department of Energy’s SAI award for equipment design for lower manufacturing costs, local and state grants, and the fact that SunPower was able to make use of an existing empty facility at Flextronics’ headquarters.

Brinser also noted the significance of being able to use an existing shell. In SolarWorld’s case, the PV manufacturer bought an existing shell from the semiconductor industry, and was able to convert it to process more than 10 million solar cells every month.

Looking out to only 2014, the predictions from the industry about where market growth will end up are wide-ranging — from 14 GW installed to as high as >45 GW. “We’re talking four years out. I’d say there’s a little uncertainly about how the market is going to develop,” Blunden said. But regardless of exactly how it turns out, the question remains, “Where do you place your bets?” Confidence in the U.S. market is key to driving more production this direction.

— Aaron Hand, SEMICON West Daily News

What a difference a year makes. Twelve months ago, attendees of SEMICON West were all too familiar with a market ravaged by the global credit crisis and semiconductor downcycle. This year, however, signs point to a healthily recovering market.

When speakers at the 2010 SEMI/Gartner Market Symposium talked forecasts, growth and expansion were repeatedly mentioned. So were change and innovation.

Suresh Venkatesan, vice president of alliance technology development, GlobalFoundriesKeynote speaker Suresh Venkatesan, vice president of alliance technology development at GlobalFoundries, emphasized the importance of collaboration in a constantly changing market. “The foundry model needs to be more collaborative to drive technology,” he said. “Individual companies no longer can handle the rising design and R&D costs, especially since chips are becoming substantially more complex because of a demand for more power.”

He explained that fewer foundries are able to compete against each other, especially for those that don’t have the scale and volume to finance such efforts. That’s where collaboration comes in. “Technology complexity has reached a point where all players have to talk to each other,” he said. “Homegrown R&D is not sustainable. We need to keep up on what’s happening on a global basis, since contract manufacturing has reached its limits.” Innovation of the collaborative process is also needed, he said.

Venkatesan identified convergence as drivers of technology along three different fronts:

• Multi-function devices will increasingly require communication capabilities, consumer functions, and computing.

• Network convergence where a common 4G-type network replaces multiple communication methods like packets and IP.

• Context convergence, like video and rich media, will place a stronger demand on what is being transmitted.

The usage of cloud computing will grow, he said, as will the use of warehouse servers. Venkatesan also sees the need for a series of devices that have processors, much like the personal smart phone. Except in this case a machine will talk to other machines, like a residential electricity meter reporting usage to a power utility.

He concluded his speech by listing three enablers for continued innovation: lithography innovation, materials enabled, and 3D-enabled scaling.

Bob Johnson, vice president of research, GartnerBob Johnson, vice president of research at Gartner, likened the industry’s economic condition as climbing out of a ravine. His outlook on the semiconductor industry showed cell phones and PCs driving the current boom. He sees very robust growth and sales in that sector through 2014, with demand currently outpacing supply.

“Memory will surge and peak in 2012,” Johnson said in regard to the equipment market outlook. Right now the biggest spenders are the major memory producers, foundries and IDMs.

“We were surprised at how rapidly the industry recovered this time,” Johnson said, referring to the dismal conditions of last year’s market. Although the market won’t return to a peak like it did in 2007, he said, it has weathered the recession and is returning to normal.

Dan Tracy, senior director, industry research and statistics at SEMI, said that today’s market is markedly different from that of a year ago, with record IC unit shipments. He recalled how the industry took a big hit in early 2009 but now is seeing strong growth in wafer shipments and noted how the majority of new investment in fabrication is in the Asia-Pacific region.

Dan Tracy, senior director, industry research and statistics, SEMIThe rising cost of gold has become a big challenge on the cost impact of packaging, Tracy said. For 2010, he predicted a 19% revenue growth for photolithography ancillary chemicals, a 17% total rise in the semiconductor materials market, and a 104% spike in spending in the semiconductor equipment market. Strong unit growth is driving the demand for materials, he said.

Gartner’s Dean Freeman, spoke about how the foundry industry has been rapidly changing over the past years, with two main technology camps — TSMC- and IBM-centric technology — battling to become the industry leader. He spoke of how leading-edge technology players should strategically position themselves to better excel in the new and challenging business environment.

SEMI’s Christian Gregor Dieseldorff discussed the trends facing fabs worldwide. His presentation looked into past trends to give an outlook through 2011. He expected 48 facilities to close in 2009 and 2010, and explained how companies that initially intended to upgrade existing facilities changed course and decided to invest in capacity.

Gartner’s Jim Walker spoke on 3D integration in the next decade. He identified how electronic systems continue to grow in complexity and how semiconductor manufacturing methods using 3D interconnects help enable fast, effective IT hardware solutions.

— Arthur Patterson, SEMICON West Daily News