Intelligence in Motion Planning as an Effective Approach to Enhancing Robot Performance

by Zlatko Sotirov, Ph.D., Senior Vice President of Engineering and Chief Scientist, Genmark Automation, Inc.

Zlatko Sotirov, Ph.D., GenmarkQ: In last year’s SEMICON West Daily News, we discussed the topic of “Bringing Intelligence to Substrate Handlers”. How do you see the robot intelligence a year later?

A: My vision about robot intelligence is consistent, and everything we said last year still holds. We made significant steps in making our robots “smarter” and able to better serve various automation needs in fabs, including implementing self-teaching, enhanced sensitivity and adaptivity to payload changes, automatic diagnostics, etc. But it seems to me that most noticeable were Genmark’s achievements in the area of intelligent motion control with an emphasis on motion planning.  Therefore, I would like to touch on key topics in the area of motion planning as well as on emerging approaches for designing robot motions in the real-world semiconductor automation environment. 

Q: Why do you consider the advances in motion planning important?

A: Everyone talks about performance enhancement, and the first and simplest thing that comes to mind is to increase the velocity and the acceleration of the robots. This in fact gives some results but not necessarily the best ones, and usually we pay a high price (increased component wear, reduced lifetime, more frequent maintenance, higher stress to the manipulated object, etc.). Therefore, I always consider this approach last, after exhausting all other more-intelligent approaches to reducing cycle time rather than speeding up the robot. In the end, if we manage to make the robot move in smoother paths that excite the robot dynamics less, there is nothing more natural than to increase the velocity and to gain additional performance. Again, this should be last on the list, after everything else has been explored. Picture it: one is trying to select the most powerful and expensive motors, paying a premium price, running these motors at high speed and through intensive and energy consuming transition periods (acceleration / deceleration phases) and at the same time unnecessarily interrupting / pausing the motion at the transition points between adjacent motion paths, provided the last are not smoothly blended together. The time gained by increasing the performance of the motors is easily lost as idle time. Of course, it is simpler that way, but way less effective and more expensive. Investing in the design of intelligent motion planning algorithms, while taking into consideration the specifics of the automation tasks in semiconductor material handling, is definitely the best investment for steadily gaining tool performance. Focusing on motion planning, we are not underestimating the importance of the high-performance direct-drive actuators and controls technologies to enhancing robot performance. In fact, the  opposite is true – these technologies demand intelligently planned motions, since there are no gears to “hide” the inertia changes and the variable dynamic loading due to motion along non-“smooth enough” paths.

Q: Staying on the motion planning subject, would you further elaborate on what in particular has been developed at Genmark Automation and what are the benefits?

A: Genmark’s first significant contribution to motion planning dates back to 1997 when we developed and implemented a unified approach to smooth trajectory planning based on high-order Bernstein-Bezier polynomials. This development was done in support to the newly introduced “Yaw” axis robots with motion dexterity which had to be adequately planned. A few years later Genmark introduced a new motion blending approach to composing smooth multi-segment trajectories in the N-dimensional space (N stands for the number of axes), eliminating unnecessary stops by overlapping the adjacent trajectory segments. The performance gain from overlapping adjacent trajectory segments and inherent motion smoothness was in the range of 20-30%. This was a significant performance benefit, but there was still room for optimizations. The approach had its own limitations. One of them was the inability to change the target position “on-the-fly” without this causing discontinuity at a velocity and acceleration level. Changing the target position “on-the-fly” was demanded by new applications requiring target correction depending on the offset of the manipulated object with respect to the end-effector, which was identified (measured) during the motion. A new motion planning algorithm addressing the above requirements has been recently developed and implemented. The benefit was, again, performance – there was no need to stop the motion after acquiring the wafer offsets and slow down the robot, since the motion smoothness was not affected by the “on-the-fly” pre-planned motion.

Another development in the same category was the design of smooth motion paths with a number of segments and a target position specified during the motion. In many material handling applications there is a need for changing the final destination of the wafer delivery during the motion, for the sake of gaining performance. Normally, if the equipment that is supposed to process the wafer is not ready in the beginning of the motion, the robot waits until the equipment becomes ready, and then starts its motion. What typically happens is that in the great majority of cases, the equipment becomes ready during the course of motion, if the motion was initiated without any wait. Therefore, the robot motion can start immediately, and if the robot receives “equipment ready” confirmation prior to reaching the approach position of the destination, it continues its motion; otherwise it stops at the approach position of the destination. The benefit of the motion planning flexibility is obvious – the robot doesn’t unnecessarily wait at start and goes to destination without stops, provided the equipment becomes ready during motion.

 Lastly, I would like to mention another advanced approach to motion planning, related to the design of smooth motion paths, composed of multiple curves with simultaneously running motion profiles. This development allowed us to significantly reduce the wafer swap-time, which has always been considered of critical importance to the performance of the semiconductor processing tools. It was determined that to optimally perform wafer-swap, dual-arm robots have to simultaneously perform (overlap) three moves compliant with the mechanical constraint imposed by the processing equipment.

 

Q: What else rather than advanced motion planning is required to achieve optimal robot performance?

 A: Motion planning is very important but is not sufficient to achieving the control goal. Planning and execution always go together. Naturally, the better the motion plan, the easier and faster the robot will follow the path, achieving the prescribed accuracy and desired dynamic behavior of the manipulated object. Robots are complex, nonlinear dynamic systems and therefore their dynamics have to be taken into consideration when building the control algorithms. If there are modeling errors or uncertainty coming from unstructured operating environment, they all have to be taken into account by the control system. As we are advancing in motion planning, we recognize the importance of the dynamic control and at the same time realize that building an accurate dynamic model under the limitations imposed by the real manufacturing environment is not an easy job. Therefore, Genmark Automation focuses significant efforts on incorporating robustness and adaptiveness into our new generation motion control systems.

 

Q: How would the advances in motion control benefit 450 mm wafer handling?

A: Naturally, the new object would impose new requirements to the material handling systems, and I wouldn’t say because of the larger wafer diameter, but because of the increased weight of the wafer itself, the weight of the bonded substrates and the weight of the fixtures (e.g. bonding fixtures) the robot may be expected to carry. In order to deliver the same or better performance as compared with the 300 mm case, the motion control system should be able to compensate for the deflection of the arm including the end-effector and for the deflection of the manipulated object. Therefore the motion paths will look differently in the vertical direction and will most probably consist of multiple segments blended together in a smooth curve, running through control points specified by the user or determined by external sensors. On the other hand, the enhanced robot sensitivity achieved through MEMS (accelerometers, inclinometers, embedded in the arm) would allow the control system to identify the payload and the dynamic properties of the manipulating system and to apply advanced deflection compensation techniques in order to achieve superior performance in compliance with the constraints imposed on the motion of the manipulated object. 

 

Zlatko Sotirov, Ph.D., is Senior Vice President of Engineering and Chief Scientist, Genmark Automation, Inc. Dr. Sotirov has 15 years academic experience in robotics and control, has made scientific and scholarly contributions in the field of robotic and control (parallel manipulators, robust and adaptive motion control, programming …), has 19 years of experience in semiconductor automation, and has been holding key developer and engineering management positions at Genmark Automation since 1994.

 

 

HORIBA Announces New PR-PD2HR Reticle and Mask Particle Detection System

HORIBA’s PD series has attained a solid reputation in semiconductor fabrication for its stability and high uptime over long periods.  Inheriting a transfer system that has proven to provide stable, high performance and superior throughput, the PR-PD2HR now offers the most sensitive detection in the standard series with exclusive signal processing that can detect particles as small as 0.35 µm.

Compatible with any stepper case, the PR-PD2HR features a multi-stage sorter that can handle up to 10 cassettes and supports a number of communication protocols. True to its colors as a member of the PD Series it boasts high capability over a broad range of general reticle and mask particle detection tasks as well as being able to evaluate glass or pellicle surfaces with high throughput. The PR-PD2HR will prove its worth by contributing to yield improvements in any semiconductor fabrication or next generation mask production facility. 

FABSURPLUS.COM SECURES 7-FIGURE ORDER FOR ADVANCED LITHOGRAPHY EQUIPMENT

Fabsurplus.com’s Web-based Marketplace enables huge savings on Semiconductor and Solar equipment for buyers looking to reduce costs.

SDI-Fabsurplus Group, a leading web-based re-marketer of advanced  equipment used to manufacture semiconductors and solar cells, today announced that Fabsurplus.com has secured a 7-figure order for advanced lithography equipment.

“Fabsurplus.com has once again achieved a major sale ahead of our competition due to our superior market intelligence, technical knowledge and customer support” said Stephen Howe, the Owner of SDI-Fabsurplus Group of Companies. “The continuing investments in our web portal at fabsurplus.com coupled with our experience in this sector since 1998 have again produced results.  We hope to leverage this success to introduce fabsurplus.com as a reliable, low-cost, alternative source for technically advanced equipment to many more clients in the near future.”

Customers can learn more about Fabsurplus.com’s re-marketing solutions during SEMICON West 2013 by contacting the Sales Team ([email protected]) who will be attending the show to promote our used semiconductor equipment solutions and our recently acquired used solar cell manufacturing lines..

According to a recent worldwide fab equipment spending forecast report by SEMI, the semiconductor equipment market size is expected to remain flat in 2013 and to grow 24% to $39.2 billion in 2014.

About Fabsurplus.com 

Fabsurplus.com refurbishes and re-markets semiconductor equipment used in the fabrication of integrated circuits. The company is a leading re-marketer of used fab equipment specializing in lithography, metrology, implant, CMP, CVD and PVD as well as Assembly, Test , SMT, FPD and Solar tool sets. Through software and design innovation, Fabsurplus.com provides technologically advanced systems and re-marketing solutions for customers fabricating current- and next-generation semiconductor devices. The company supplies equipment and provides re-marketing solutions to foundries, power device , memory and logic integrated device manufacturers in the United States, Europe, China, Japan, Korea, Singapore, Taiwan and other Asian countries. The website Fabsurplus.com receives 700,000 visits yearly.

For more information, please contact SDI-Fabsurplus LLC, 1001 S Main Ste 3, Boerne TX 78006. Telephone: +1-830-388-1071. Internet: www.fabsurplus.com. 

Silicon Innovation Forum

The Silicon Innovation Forum will bring together new and emerging companies with the semiconductor industry’s top strategic investors and leading technology partners. This innovative forum will include a conference (open to all SEMICON West attendees) featuring a keynote presentation, panel discussion on the industry’s innovation pipeline, and the Pitch Zone, a dynamic session consisting of short presentations on exciting new business opportunities and technology ideas from a diverse collection of new and emerging companies. The SIF Innovation Showcase and Networking Reception is a private event immediately following the conference and will include one-on-one opportunities to meet with the industry’s leading strategic investors, venture capital companies, and other potential investment partners.

 

Tuesday, July 9, 2013

Moscone Convention Center, Esplanade Hall (Keynote Stage)

1:00–4:45pm SIF Conference

3:00–6:30pm SIF Innovation Showcase and Networking Reception

 

Silicon Innovation Forum Presenters and Companies

John D. Heaton, Executive Vice President and General Manager, Advenira (Materials)

John Brewer, CEO and President, Amorphyx (Flexible Electronics)

Eryn Smith, CEO, Beam Services, Inc. (Equipment Supplier)

Bob Lloyd, CEO, BrightSpec, Inc. (EUV/Inspection Metrology)

Scott Grimshaw, CTO, Colnatec (Equipment Supplier)

Paul Blackborow, CEO, Energetiq Technology, Inc. (Sub-Assembly/Components)

Brenor Brophy, President & CEO, Enki Technology, Inc.

Marianne Germaine, CEO, EpiGaN (Materials)

Richard B Brown, CEO, e-SENS (Silicon-based chemical sensors)

Andrew Grenville, CEO, Inpria (Materials)

Sujatha Ramanujan, COO, Intrinsiq Materials Inc. (Materials)

Zvi Or-Bach, President & CEO, MonolithIC 3D Inc. (Intellectual Property)

David Mather, President & CEO, MTPV Power Corporation (Materials, Equipment Supplier, Sub-Assembly/Components, Services)

Bala Vishwanath, CEO, Nimbic (Electromagnetic Simulation For SI, PI and EMI)

Gianpiero Tedeschi, CEO, Noivion Srl (Equipment Supplier)

Craig Bandes, President and CEO, Pixelligent Technologies LLC (Materials)

Rob Randhawa, Founder / CEO, Planar Semiconductor (Equipment, 450mm, defect control)

Lynn Forester, CEO and Co-Founder, Quantum Semiconductor LLC (Materials)

David Ferran, CEO, Reno Sub-Systems (Equipment, on-tool gas delivery system)

Boris Kobrin, CEO, Rolith, Inc. (Equipment Supplier)

Hash Pakbaz, President & COO, SBA Materials, Inc. (Materials)

Dadi Gudmundsson, President, Sensor Analytics (Services, Software)

Carl Griffiths, CEO, Seren Photonics Ltd (Materials, Services, Provide IP to Fab Level companies)

Rajiv Singh, Founder and CTO, Sinmat Inc (Equipment, 450mm, planarization)

Ryu Shioda, CTO, Wafer Integration Inc. (Equipment Supplier)

 

M0QgSUNzIOKAkyBTdGlsbCBKdXN0IEFyb3VuZCB0aGUgQ29ybmVy

By Jeff Dorsch

Three-dimensional integrated circuits are right around the corner. No, wait, they aren’t. Check that – they’re definitely on the way. It all depends on what kind of 3DICs you’re talking about.

Stacked-memory technology – that’s here and now. Silicon interposers – check, double check, triple check. But logic and memory integration in one 3D package? That’s a whole other thing.

The path to realization of 3DIC technology has led to a curious term: 2.5D, to indicate that it’s not quite 3D, but more advanced than the traditional 2D packaging. With 2.5D, two chips basically make a sandwich with a silicon interposer between them, employing system-in-package technology.

Lode Lauwers, imecLode Lauwers, vice president of business development at imec, the Belgium-based microelectronics and nanoelectronics research organization, says of 3DIC technology, “Yes, it’s slowing down, but it absolutely will happen.” Many in the semiconductor industry “underestimated” how complex and difficult the technology has proven to implement, he notes. “It’s not just a good TSV [through-silicon via]. You need to be able to test it,” Lauwers says.

While 3DIC technology beyond stacked memories is proceeding “a little bit slower,” Lauwers asserts, “We’re fully confident it’s going to happen.” He looks for the leading silicon foundries to begin volume production of 3DICs in 2014 or 2015, following prototype production. “By the end of the decade, we will have steps nearly complete,” Lauwers adds.

For companies that make semiconductor inspection and metrology equipment, such as KLA-Tencor, 3DICs are presenting a substantial technical challenge, according to Brian Trafas, the company’s chief marketing officer. “You need to be able to detect particles, bridging,” he says. “Customers are interested in not only a top-down structure, but sidewall construction…the top, bottom of the trench.”

The complexity of process steps in 3DIC structures, along with the increased number of process steps, means process control in the 3DIC era will mean “a higher spend rate,” Trafas says. “KLA-Tencor and some of our competitors are seeing that.”

Sesh Ramaswami, managing director of TSV and advanced packaging/advanced product technology development in the Silicon Systems Group of Applied Materials, sees 3DIC structures coming along in a gradual process. “From a technology point of view, TSV has borne out,” he says. “That takes the first hurdle out of the way. It’s like any new technology; you have to work things out.”

It’s natural to have “some bumps along the way,” Ramaswami says – and we don’t mean wafer bumps.

The Applied executive sees three approaches to 3DIC structures contending in the industry – the Hybrid Memory Cube, JEDEC’s Wide I/O standard and the high-bandwidth stack. Ramaswami sees logic and memory integration in 3DICs going into volume production in two years.

“Most of the work on the TSV has been how to make it smaller [for mobile applications],” he notes. “That’s no show-stopper.”

Temporary bonding of substrates to a carrier of glass or silicon is a key development in 3DIC technology, Ramaswami says. “For the last three to four years, people have been working on that,” he adds.

The multichip modules of two decades ago don’t compare with what is being done in 3DIC structures, according to Ramaswami. MCMs represent 2D integration, not 3D, he asserts. The ceramic substrates of MCMs proved to be “expensive,” he says. With silicon interposers, the ceramic material is replaced with silicon, the Applied executive notes. An interposer, he says, is essentially “an MCM on silicon.”

For Risto Puhakka, president of VLSIresearch, the market research firm, says that when it comes to 3D integration, “there’s been way too much talk, compared with results. There are benefits with 3D, but there are also limitations.” For signal integrity, “yes, it absolutely makes sense,” he notes. Such structures also offer speed advantages, he adds.

But when it comes to “beating Moore’s Law, it’s not economical,” Puhakka says.

Paul Lindner, EVGroupPaul Lindner, executive technology director for EV Group, says of 3DIC structures, “A system needs to be designed around 3DIC. You can’t just drop in memory chips.” True system integration with 3DIC technology “requires close integration with the microprocessor or logic,”

Temporary bonding “is not fully realized,” he says. “Only in the past one to two years, interposers became more important. Now they are on top of the list.” Interposers are “needed for stacking memories, microprocessors, logic devices,” Lindner says.

The EV Group executive says, “We believe in the performance benefits of 3DIC. We think it will come. It will be a key enabling technology to expand Moore’s Law in a cost-effective way without shrinking [IC dimensions].”

A session devoted to “Advancing 2.5D and 3D Packaging through Value Engineering” will be presented at TechXPOT North, in the North Hall of Moscone Center, at 1 p.m. on Wednesday, July 10.

The program summary states, “Growing industry requirement for vertical and heterogeneous integration, as well as related packaging strategies, remains a crucial focus for many forward-looking semiconductor supply chain players. While the implementation timeline of true 3D packaging with TSV technology has been pushed out for many applications, a number of highly innovative solutions for interposers (2.5D) are already hitting the market. However, improving process yield and lowering the cost relative to alternatives are proving resilient bottlenecks to mainstream 2.5D and 3D packaging. Clearly, headway hinges on the delivery of value appropriate to the function.

“For an industry seeking progression of 2.5D, as well as an effective value/function equation for 3D, it appears that success can partly be found in the innovation and evolution of equipment and materials. This session will take a critical look at supply chain ecosystem participants who are pioneering tools and materials, exclusively geared towards high-volume implementation of 2.5D and 3D packaging.”

Keynote addresses in the Wednesday session will be given by executives from Altera, the Association of Super-Advanced Electronics Technologies and the KPMG Global Semiconductor Practice. The keynotes will be followed by an infrastructure panel session with executives of Amkor Technology, ASE Group, Hitachi Chemical, STATS ChipPAC, TEL NEXX and United Microelectronics Corp.

Three-dimensional films are a hot trend in movie theaters, although 3D video on television hasn’t enjoyed much adoption. For 3DIC structures in semiconductors, there may be comparable levels of mixed success.

 

450mm Progress Update

By Jeff Dorsch

 The semiconductor industry’s transition to manufacturing on 450-millimeter silicon wafers is coming, whether you like it or not. It’s time to get on the bandwagon or to watch the parade.

At the same time, it is clear that only a small number of chipmakers will initially take the plunge into 450mm wafer fabrication. This transition in substrate diameters may go on for some years before it takes hold throughout the industry.

Suppliers of front-end and back-end production equipment have been hard at work for years already, updating their product lines to handle 450mm wafers. Silicon wafer manufacturers have been at it, too, to provide the necessary blank substrates.

Brian Trafas, KLA-TencorBrian Trafas, chief marketing officer of KLA-Tencor, says his company and others have “a lot of interest in helping with the transition.” Semiconductor manufacturers want to “make sure the yield is better on the larger substrate,” he adds. The bounty in extra chips per wafer is a key consideration, too.

“We help wafer manufacturers with the quality of the wafers they’re making,” Trafas notes. The industry roadmap calls for 450mm wafer fabrication to begin in 2018, he says. “Wafer manufacturers need to make wafers long before that,” he observes.

KLA-Tencor began developing 450mm-capable process control and yield management equipment “four or five years ago,” Trafas says. A year ago at SEMICON West, the company announced the first installations of the Surfscan SP3 450, a 450mm-capable unpatterned wafer inspection system. “We sold some to wafer manufacturers,” Trafas reports.

For now, KLA-Tencor is “focusing to continue to strengthen our (450mm) portfolio,” he adds.

Kirk Hasserjian, Applied MaterialsKirk Hasserjian, vice president of strategic programs for the Silicon Systems Group of Applied Materials, gives general details about his company’s activities in 450mm-capable wafer processing equipment, while not giving away too many specific details. “We’ve got activities ongoing to what our customers need,” he says. “We’re trying to stay close to our customers, the key customers who are driving it.”

Unlike the days of transitioning from 200mm wafer fabrication to 300mm, “the industry is highly synchronized” now, Hasserjian says. The industry now has a keen financial interest in making certain that “R&D dollars being put into 450 are invested in the right way,” he adds.

The Global 450 Consortium is coordinating many efforts around development of 450mm wafer fabrication, the Applied executive says, and Europe is seeing “a number of activities” in the field, at imec and elsewhere, he notes. SEMI and SEMATECH contributed 450mm standards early on, and “that helps quite a bit,” Hasserjian says.

While a number of 450mm consortia in addition to G450C have sprung up around the world, “I don’t see things coming up as conflicting,” Hasserjian notes. “That was true of 300 millimeter.”

Risto Puhakka, VLSIresearchRisto Puhakka, president of VLSIresearch, the market research firm, isn’t as sanguine about the progress of the 450mm transition. “Intel is the proponent of 450 millimeter,” he says. “I don’t see Samsung, TSMC moving on it. It’s pretty hard for the equipment guys, with one customer. The other guys aren’t moving along.”

Still, “the programs are moving,” Puhakka adds. Taiwan Semiconductor Manufacturing, the world’s largest silicon foundry, plans to have 450mm fabs up and running in 2016, he notes.

Two years ago, EV Group introduced the EVG850SOI/450 mm system for bonding 450mm wafers made from silicon-on-insulator substrates. Soitec took the first delivery of the system in 2011. To handle the multiple types of technology used in the industry, “we have three to four process models in process,” says Paul Lindner, executive technology director at EV Group. “They will be made available soon.”

In the future of back-end equipment, wafer-level package assembly “will be highly important with 450 millimeter,” he says.

Due to the larger size and weight of the substrates, wafer handling must be completely automated for 450mm wafers, according to Lindner, with automated wafer loading into equipment, fully automated front-opening unified/universal pods (FOUPs) and robotics.

At SEMICON West this year, there are several programs where the 450mm transition will be discussed. On Wednesday, July 10, a session called “Silicon Wafers – Future Standardization to Enable the Transition” will be held at the Marriott Marquis Hotel, beginning at 2:30 p.m. The program summary notes, “Since 2008, SEMI has published fifteen 450mm wafer standards, guided by customer requirements and supplier feedback. These specifications, covering wafers, carriers, and loadports, have enabled the industry to continue the development of equipment, materials, interfaces, and processes, but further standardization will be necessary for a successful transition to manufacturing on 450mm wafers.”

On Thursday, July 11, the SEMICON West 450mm Transition Forum will be at 10:30 a.m. at TechXPOT South, in the South Hall of Moscone Center. The forum will include presentations by Kirk Hasserjian of Applied Materials, Paul Farrar of the Global 450 Consortium, Brian Trafas of KLA-Tencor, Hamid Zarringhalam of Nikon Precision, Chris Richard of PricewaterhouseCoopers, Jonathan Davis of SEMI and Akihisa Sekiguchi of Tokyo Electron Ltd.

The program summary says, “Increased levels of collaboration, further advancements in tool prototypes, and increased visibility into related supply chain implications have occurred over the past year as the semiconductor industry implements the capability to manufacture its products on 450mm wafers.  The SEMICON West 450 Transition Forum will provide the latest updates on the status of 450 R&D, as well as a review of key technology considerations and a discussion of implications and opportunities for the supply chain.”

The 450mm transition, as some have noted, is proceeding in a more orderly, cooperative process than the 300mm transition, which suffered from top-down dictation to semiconductor equipment and materials vendors. It remains to be seen whether those vendors will feel better about 450mm than they did about 300mm in the beginning, when they had to absorb research and development costs that weren’t rewarded with orders for 300mm equipment.

Update: Significant Progress on EUV

By Jeff Dorsch

What a difference a year makes!

Twelve months ago, the industry handwringing over the slow progress of extreme-ultraviolet lithography was widespread. Discussions of the attributes (and limitations) of directed self-assembly and double-patterning lithography were common.

Today, extreme-ultraviolet lithography isn’t completely out of the lab and into the fab yet, but the good news is that it’s on the way.

The turning point, it seems, was the SPIE Advanced Lithography conference in late February, where Cymer reported significant progress in improving the wattage of its laser power source for EUV systems.

“In addition to the good news of EUV source power achievements, there were first signs of considerations for EUV adoption in high volume, coming from infrastructure development such as EUV mask actinic inspection, EUV mask OPC, and EUV lithography integration in a full CMOS flow with yield-defectivity investigations,” Mircea Dusa of ASML US said in an SPIE statement.

ASML’s current TWINSCAN NXT 1950i lithography tool for HVMSince then, ASML Holding has completed its $3.7 billion acquisition of Cymer, its long-time partner in EUV source development. Ryan Young, senior manager of communications at ASML, says that the Cymer laser source has been bumped up to 60 watts in the past four months, with a prospective throughput of 39 wafers per hour for the accompanying EUV system. “That is a marked improvement over the last year,” he comments.

The system has been able to produce linewidth spaces of 13 nanometers and holes of 17nm, with resolution down to 9nm, according to Young. “Overlay and imaging are performing ahead of specs,” he says.

The remaining measure of progress, Young adds, is productivity.

ASML had multiple reasons to acquire Cymer, Young notes. “ASML and Cymer collaborated very closely for many years,” he says. The laser serves as “a sparkplug” for the EUV system, turning tin droplets into a plasma, he notes.

“It comes down to they’re a separate company,” Young says of the status between the companies before the acquisition agreement was announced in October of last year. “They have a fiduciary duty to their shareholders.” ASML and Cymer had to operate at arm’s length for a variety of reasons to protect their proprietary interests.

“Acquiring them reduced these barriers,” Young comments. “We took a perfectly good relationship to a seamless one.”

For years, developing lithography systems could be the province of one leading technologist at an equipment vendor, with little or no help from outside the company. That approach worked in the step-and-repeat and step-and-scan era of lithography, according to Young.

The increasing complexity of advanced lithography has called for a team approach to system design and manufacturing, he adds. “That’s what it’s going to take to get this done,” he says of EUV development.

ASML has no plans for a big announcement at SEMICON West, “nothing earth-shatteringly new,” Young says. “We will share data.” The company is aiming to achieve throughput of 70 wafers per hour in the second half of 2013, he adds.

“This is really, really hard stuff,” Young concludes. “Progress is being made. We expect that to continue.”

Skip Miller, ASML’s director of strategic marketing, is scheduled to be one of the speakers in a TechXPOT South session at 10:30 a.m. on Wednesday, July 10. The program summary for “Still a Tale of Two Paths: Multi-patterning Lithography at 20nm and Below: EUVL Source and Infrastructure Progress” says, “Though progress to take EUVL into the realm of high-volume manufacturing continues to be made, the readiness of the source technologies to take on HVM are still not known with a high degree of certainty. The challenges facing source development are still average power, dose stability and uptime. EUV mask and resist infrastructure readiness activities must also come together in time and address such challenges as defect density (for masks), and line edge roughness, sensitivity, and resolution for resists. No doubt, there will be multiple opportunities to insert EUVL into lower volume production lines — such opportunities will be based on specific products and device applications. Until EUVL is ready for HVM, the industry must continue to rely on double-patterning and even multiple-patterning lithography schemes using 193 immersion lithography to take it beyond 22nm. Speakers will present the current status of EUVL readiness, as well as discuss the current plans and challenges of extending 193i with double and multiple-patterning.”

Earlier on Wednesday morning, 8 a.m. at the San Francisco Marriott Marquis, SEMI and SOKUDO will present the Lithography Breakfast Forum, with speakers from ASML, Canon, Molecular Imprints, Nikon, SOKUDO and Ultratech.

Nikon Precision, the industry’s long-time lithography leader, has been concentrating on immersion and multi-patterning lithography equipment. The company is planning to have argon fluoride immersion system prototypes, capable of handling 450-millimeter wafers, in the 2015-16 timeframe.

Risto Puhakka, president of VLSIresearch, the market research firm, says “Progress is really good” on EUV technology. For ASML, “laser power has been very, very promising,” he adds. The company is “committing to 100 wafers per hour” by the end of 2014, Puhakka says. “They’re moving along really well.”

When it comes to serious EUV development, it’s “ASML and its customers – no one else,” Puhakka says. Those customers are principally Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing, which each have made equity investments in ASML.

Lode Lauwers, vice president of business development for imec, says lithography is “one main challenge” for the contemporary semiconductor industry. “We are very much working on EUV,” he adds, along with double-patterning technology. “There are, at last, big improvements now with EUV,” he adds. When it comes to higher throughput, “new data points on the new generation will be coming in this year,” he says.

By late 2013 or early 2014, “we will know more about EUV,” Lauwers predicts.

KLA-Tencor’s chief marketing officer, Brian Trafas, says his company “plays an important role in the lithography industry because we are a world leader in reticle inspection.” For EUV, “you need a scanner with the right sources to get the throughput,” he adds. “We are working with the industry to inspect EUV masks.”

KLA-Tencor is conducting R&D on a EUV mask inspection system for high-volume manufacturing, according to Trafas.

Extreme-ultraviolet lithography has made impressive gains since SEMICON West in 2012. What can be accomplished in the next 12 months will be critical to the future of EUV.

 

Top Tier MEMS Fab Selects ClassOne Equipment Refurbished Spray Solvent Tool

ClassOne Equipment announced today that it has recently sold, installed, and released into production a fully refurbished SEMITOOL Spray Solvent Tool (SST) at a top tier, US based MEMs Fab for its resist strip process. 

“Our decision process was rigorous and based on many factors including:  process performance, tool reliability, long-term support, and of course price.” said the Sr. Engineer responsible for selecting this system.  “In the final analysis, the value proposition was compelling to us. We saw a clear benefit in buying a remanufactured SST from ClassOne over a new tool, or a used tool from other suppliers.”

Win Carpenter, Vice President of ClassOne’s Wet Process Division stated “For over a decade, the SEMITOOL SST has been the tool of choice for solvent processing in semiconductor fabrication applications ranging from resist strip to metal lift-off.   Given the appropriate level of refurbishment, these tools are still relevant today, especially in emerging technology sectors like MEMs, LED, Power and RF Devices. “  Carpenter further added, “ClassOne Equipment has established a leadership position in the refurbishment, service, and support of SEMITOOL systems through its recent expansion of factory-trained personnel, system and sub-system refurbishment capabilities, as well as service and parts offerings.”

Byron Exarcos, President of ClassOne Equipment, added “This is a great example of ClassOne Equipment establishing a footprint in yet another top tier MEMs fab.  We are confident that our continued focus on our Wet Process Division will provide ever-increasing value to our customers worldwide. “

About ClassOne Equipment

ClassOne Equipment (http://ClassOneEquipment.com) is a recognized leader in the business of equipment refurbishment with over 2,500 tools installed world-wide in four key markets:  Semitool Wet Chemical Processing, SPTS Plasma Etching & PECVD, Suss/EVG Mask Aligners, and KLA-Tencor Wafer Inspection.   Known for superior quality 75 to 300mm equipment, customer-first service, and its 30-day unconditional return policy, the ClassOne team has been winning and serving customers in the traditional semiconductor and emerging technology sectors for over 10 years. 

For more Information Contact:

Byron Exarcos

ClassOne Equipment

770.808.8708

 

CLASSONE EQUIPMENT EXPANDS WET PROCESSING DIVISION

Establishes ClassOne Technology as New Design and Development Subsidiary

Atlanta, GA – July 9, 2013 – ClassOne Equipment announced today that it has made significant investments in the growth and expansion of its Wet Processing Division in response to increased market demand.   A Design and Development Center has been opened in Kalispell, Montana, staffed with several veterans who represent over 200 years of cumulative industry experience, who will focus on new product design and development.   Corporate and refurbishment activities will remain at ClassOne’s headquarters in Atlanta, Georgia.

“We are thrilled with the strong customer response to ClassOne’s industry-leading products and support.  We have expanded the division to enhance our sales and support of legacy Semitool® equipment worldwide as well as to design and manufacture new state of the art upgrades and platforms that address emerging markets such as MEMS, Nanotech, LED and RF Power Devices,” said Byron Exarcos, ClassOne’s President.  “Semitool’s acquisition left a void in the market for mature fabs and emerging technologies that use 75 to 200mm substrates.  ClassOne is meeting the growing demand for cost effective, reliable, and long-term support for popular tools such as the Equinox®, LT210C, Raider®, Spray Solvent, and Spray Acid tools.  The wide-spread adoption of our lift-and-rotate and robot refurbishment programs gives testimony to that fact.”

The new facility in Kalispell will be operated under the name of ClassOne Technology as a wholly owned subsidiary of ClassOne Equipment.  The executive team includes:  Win Carpenter, a 33-year veteran in the Semiconductor Industry, VP Wet Process Division; Tim McGlenn (26 years experience, including leading the software and electronics development of Semitool’s 101, 102, 202, 302, 402 and 502 controllers), VP of Operations; and Kevin Witt (25 years focused on the development and commercialization of new wet chemical processing platforms), VP Technology; all of whom previously held leadership positions at Semitool.  Their appointment further strengthens the division, positioning it for enhanced growth and continued market leadership.

ClassOne Technology’s first product, the PolarisTM controller, is an advanced, PLC-based, field-retrofittable control system that replaces the aging 302 control system used in many Semitool legacy tools.  The Polaris controller will be unveiled at SEMICON West in San Francisco from July 9th through 11th where it will be demonstrated in a fully refurbished Semitool Spray Solvent Tool exhibited at ClassOne’s booth (#441).

ClassOne Equipment (http://ClassOneEquipment.com) is a recognized leader in the business of equipment refurbishment with over 2,500 tools installed world-wide in four key markets:  Semitool Wet Chemical Processing, SPTS Plasma Etching & PECVD, Suss/EVG Mask Aligners, and KLA-Tencor Wafer Inspection.   Known for superior quality 75 to 300mm equipment, customer-first service, and its 30-day unconditional return policy, the ClassOne team has been winning and serving customers in the traditional semiconductor and emerging technology sectors for over 10 years.

 

For more Information Contact:

Byron Exarcos

ClassOne Equipment

+1 770.808.8708

HORIBA ANNOUNCES NEW CRITERION SERIES D500 MASS FLOW MODULE

For the most critical semiconductor gas delivery requirements, HORIBA STEC introduces the D500 Mass Flow Module. Extending the Criterion technology from the highly accurate and reliable D200 series, the D500 provides unparalleled accuracy and repeatability while providing self-diagnostics, high-turn down capability, and line pressure insensitivity.

Developed utilizing the most advanced gas metrology facilities and technologies, the D500 will aid equipment and process engineers with the chamber matching process by using the D500’s internal diagnostics to ensure that the gas delivery system remains accurate and repeatable. Please come by SEMICON West 2013 booth 1819 for a demonstration.