MYSEMICONDAILY EXECUTIVE INTERVIEW: THOMAS ENGSTEDT, CEO, ADVANCED VACUUM – A PLASMA-THERM COMPANY

Thomas Engstedt, CEO, Advanced VacuumQ: What is your business segment, product, and approach?

A: We have created a compact and reliable tool which is very capable and affordable in the very competitive R&D market.  The tool was developed with the capabilities of the highly respected SLR technology developed by Plasma-Therm, our parent company.  The SLR tool is one of the most reliable and capable tools in use by labs, universities and institutions world-wide.  The Apex SLR takes advantage of the features of the SLR and is repackaged in a compact form factor using all digital communication and the best-of-breed components available today.

Q: What was your goal with this product?

A: We provide an ICP tool to develop processes and methods for etching compound and mainstream semiconductor materials for potential transfer to mainstream device production.

Q: How is your product or approach different from your competition?

A: The Apex SLR is smaller, more reliable and affordably priced.  Leveraging years of proven SLR processing capabilities, the Apex SLR will allow users to continue the legacy of a reliable platform, known process capability and a service and support network that has been recognized for 15 years as the “Best of the Best”.

Q: How is your product or approach better than your competition?

A: Besides the well-established process capabilities of the SLR technology, the Apex SLR was developed to accommodate specific needs for the R&D market.  These would be: High reliability, small footprint, ease of use, repeatable processing and ease of serviceability; all at a very competitive and affordable cost.

Q: What changes or shifts (business / technical) do you see coming in this product segment?

A: The R&D and Failure/Yield analysis markets require a tool that is easy to use, is available for processing when needed.  Tool reliability, flexibility, capability and dependability will drive the market for years to come.

Q: How will you help customers address those shifts?

A: We have addressed these issues with forward thinking design and capabilities already designed into the tool.  If there is a failure, customers do not want to spend time taking off covers and weeding through a jungle of wires and components to get the tool operational.  With best-of-breed components and packaging that makes sense with easy access, the Apex SLR is already designed and built with today’s needs and tomorrow’s possibilities.

HORIBA Company Profile

The HORIBA Group of worldwide companies provides an extensive array of instruments and systems for applications ranging from automotive R&D, process and environmental monitoring, in-vitro medical diagnostics, semiconductor manufacturing and metrology, to a broad range of scientific R&D and QC measurements. Proven quality and trustworthy performance have established widespread confidence in the HORIBA Brand.

Supporting the evolution of smart life styles with high-precision technologies, HORIBA Semiconductor  offers a comprehensive range of control and analytical solutions to improve yield, increase throughput, and add value to the Semiconductor, Flat Panel Display (FDP), Light Emitting Diode (LED),  Photovoltaic (PV) and related manufacturing and research industries.

From advanced high-accuracy Fluid Delivery technology to such diverse applications as wet process, dry process, lithography metrology and process monitoring, HORIBA is the global leader in bringing scientific expertise and industry know-how together to produce critical technologies required for tool matching, recipe creation, and the final goal of maintaining a stable process by using advanced process control.

HORIBA’s special blend of global companies, technologies, and culture are bringing creative solutions to the problems of designing the next generation processes that have been essential to the advancements made in semiconductor technology.

Inspired by our unique motto, “JOY and FUN,” we focus on social responsibilities by building state-of-the-art products for scientific advancement; especially for protecting health, safety, and the environment. “HORIBARIANs,” the HORIBA employees all over the world, are looking forward to working with you and providing the best analytical and process control solution for your needs. Please visit us at SEMICON West 2013, booth 1819.

 

New Directions in Flexible Electronics

FleX Silicon-on-Polymer IC (Source: American Semiconductor)How will the industry confront the challenges to move printed/flexible electronics into real markets?  With the market for printed and flexible electronics projected around $176 million this year but targeted for 27% CAGR to about $950 million by 2020, SEMICON West is helping the industry begin to mobilize and respond to the challenges.

Developers have made major progress in the technology to manufacture printed or flexible circuits, sensors, batteries and displays. But it’s hard to build applications with much market pull without logic or memory as well, and those have been much harder to make. However, now printed memory and solutions for integrating conventional silicon die into flexible systems are edging into production to potentially improve performance for a wider range of applications.  On the display side, easily integrated printed or flexible transparent conductive films for touch screens are starting to see some market traction.  

Attend “Integrating Conventional Silicon in Flexible Electronics” at the Extreme Electronics TechXPOT, Moscone Center, South Hall (Thursday, July 11 from 10:30am-1:10pm).  The FlexTech Alliance program includes:

– Douglas R. Hackler, American Semiconductor, on “FleX™ Silicon-on-Polymer: Flexible Electronics from Conventional Silicon ICs”

– Quyen Chu, Jabil, on “Investigation of Components Attachment onto Low Temperature Flex Circuit”

– Dahwey Chu, Sandia National Laboratories, on “Electronic in the Prototyping of Flex Systems”

– Yung-Yu Hsu, MC10, on “Reshaping Electronics for the Human Body”

– Chandrasekhar Durisety, Thin Film Electronics on “Introduction to Thinfilm Technology”

 

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Thomas Engstedt, CEO, Advanced VacuumQ: What is your business segment, product, and approach?

A: We have created a compact and reliable tool which is very capable and affordable in the very competitive R&D market.  The tool was developed with the capabilities of the highly respected SLR technology developed by Plasma-Therm, our parent company.  The SLR tool is one of the most reliable and capable tools in use by labs, universities and institutions world-wide.  The Apex SLR takes advantage of the features of the SLR and is repackaged in a compact form factor using all digital communication and the best-of-breed components available today.

Q: What was your goal with this product?

A: We provide an ICP tool to develop processes and methods for etching compound and mainstream semiconductor materials for potential transfer to mainstream device production.

Q: How is your product or approach different from your competition?

A: The Apex SLR is smaller, more reliable and affordably priced.  Leveraging years of proven SLR processing capabilities, the Apex SLR will allow users to continue the legacy of a reliable platform, known process capability and a service and support network that has been recognized for 15 years as the “Best of the Best”.

Q: How is your product or approach better than your competition?

A: Besides the well-established process capabilities of the SLR technology, the Apex SLR was developed to accommodate specific needs for the R&D market.  These would be: High reliability, small footprint, ease of use, repeatable processing and ease of serviceability; all at a very competitive and affordable cost.

Q: What changes or shifts (business / technical) do you see coming in this product segment?

A: The R&D and Failure/Yield analysis markets require a tool that is easy to use, is available for processing when needed.  Tool reliability, flexibility, capability and dependability will drive the market for years to come.

Q: How will you help customers address those shifts?

A: We have addressed these issues with forward thinking design and capabilities already designed into the tool.  If there is a failure, customers do not want to spend time taking off covers and weeding through a jungle of wires and components to get the tool operational.  With best-of-breed components and packaging that makes sense with easy access, the Apex SLR is already designed and built with today’s needs and tomorrow’s possibilities.

 

Are Diamonds the Next-Generation of Semi Materials?

By Jeff Dorsch

Innovations in semiconductor technology call for materials that can meet the technical challenges of advanced devices. Integrated circuits are a key part of what’s going on in mobile devices and other electronics, of course, while light-emitting diodes are also becoming critical to a wider variety of products.

“It goes back to your R&D group. If you’re not innovating, you’re dead,” says Craig Borkowski, optical segment leader for Momentive Performance Materials. “As you see, the chip sizes continue to decrease.”

Momentive offers highly thermally conductive materials used in both LED and semiconductor packaging. When it comes to LEDs, “you have to be careful in your design, to get as much brightness as possible,” Borkowski says.

“For Momentive, it’s going pretty well both on the semiconductor side and the LED side. We’re definitely seeing a recovery this year,” he adds. The company just opened a technology center in South Korea, where Borkowski is based. “We see a pretty bright future in electronics,” especially in automotive systems, he says. “It’s pretty amazing how much electronics is being stuffed into vehicles.”

LEDs are more than just blinking lights on various electronics products. They’ve been incorporated into flat-screen televisions, and “now they’re replacing incandescent light bulbs,” Borkowski notes. “We expect that area to explode as well.”

In LED and organic LED materials, Momentive’s leading competitors are Dow Chemical and the Shin-Etsu MicroSi subsidiary of Shin-Etsu Chemical, according to Borkowski. On the semiconductor packaging materials side, the company’s leading rivals are Henkel, Hitachi Chemical, and Sumitomo Chemical, he says.

Momentive was formed in the 2006 sale of General Electric Advanced Materials to Apollo Management, including the GE Bayer Silicones and GE Toshiba Silicones joint ventures. Four years later, the GE materials business was combined with Hexion Specialty Chemicals to form Momentive Performance Materials Holdings, which contains Hexion and Momentive.

Momentive last month said it was expanding its production facilities in Texas City, Texas, and Leverkusen, Germany. The Leverkusen plant makes silicones and has a technology center, along with application development centers for its customers.

Thermally conductive materials are a big deal at Element Six, a De Beers Group company formerly known as De Beers Industrial Diamonds. The sixth element, of course, is carbon, the basis for diamonds, mined or synthetic.

According to Adrian Wilson, head of the Technologies business at Element Six, the company’s synthetic diamond supermaterials can function as a heat spreader in IC packages, among other applications. In addition to the Semiconductor segment, the Technologies business also has an Optical segment, which makes synthetic diamond optical windows (or lenses) for high-power lasers, as used in extreme-ultraviolet lithography equipment and other applications. “Diamond is an excellent conductor of heat,” Wilson says. He adds, “It has five times the thermal conductivity of copper.” (That’s element 29, by the way.) “Zinc selenide will break down at high temperatures,” Wilson notes. “You don’t have that issue with diamond.”

Element Six produces its synthetic diamond supermaterials with a chemical vapor deposition process. The diamond material “enables devices at higher power densities,” Wilson says.

In May, Element Six announced its acquisition of the assets and intellectual property of Group4 Labs, a supplier of gallium nitride-on-diamond semiconductor materials for radio-frequency (RF) and high-power devices. The Group4 technology could help the company demonstrate how GaN-on-diamond could potentially be more useful and reliable than gallium nitride or silicon carbide on their own, according to Wilson. “There will be certain applications where diamond does offer the potential for more rapid adoption of these materials,” he says.

Asked how diamond supermaterials or GaN-on-diamond compares with silicon-on-sapphire technology, Wilson replies, “Generally speaking, diamond has a higher thermal conductivity than sapphire.” Silicon-on-sapphire, once confined to military/aerospace semiconductors, is becoming more widely used in high-performance RF applications.

Element Six is the biggest producer of microwave CVD diamond in the world, Wilson asserts, and the company has opened a manufacturing facility in Santa Clara, Calif. – close to Intel headquarters – in addition to its high-volume plants in the Netherlands and the United Kingdom.

In addition to lasers for EUV systems and semiconductor materials, Element Six is working on future applications of synthetic diamond supermaterials, both short term and long term. “We have a number of patents in the diamond development area,” Wilson notes.

When it comes to EUV lasers, “the more laser power you can generate, the better the throughput of EUV,” the Element Six executive says. “We are part of the overall supply chain for EUV manufacturers,” he adds, and that includes ASML Holding, the leading maker of EUV equipment in the world, which this year acquired its laser-source supplier, Cymer.

Diamond is also used for mounting ICs in multichip packages, Wilson says. It is “an extremely good insulator,” he comments, and its use in more common types of semiconductor packaging is rising.

Longer term, Element Six’s Optics business is working in the field of quantum encryption, a technology that is part of the process of realizing a quantum computer. “We’re working on some (U.K.) government programs on quantum repeaters,” Wilson says. Quantum encryption is relatively “close to hand” in realization, while quantum computing is further out, perhaps a decade away, he forecasts.

SEMICON West will see a program on next-generation materials presented on Tuesday afternoon, July 9, at the TechXPOT in the South Hall of Moscone Center. GlobalFoundries is sponsoring the two-hour session, which is titled, “Materials Growth Opportunities at Both Ends of the Spectrum.” The program is hosted by SEMI’s Chemical & Gas Manufacturers Group.

Dan Herr, professor and chair of the Nanoscience Department at The Joint School of Nanoscience and Nanoengineering in Greensboro, N.C., will open the program with his keynote address. The session will feature presentations by Richard Dixon of Intrinsiq Materials, Christophe Fitamant of Yole Développement, Paul Besser of GlobalFoundries, and Mark Thirsk of Linx Consulting.

These days, there is more to semiconductor materials than planar silicon and complementary metal-oxide semiconductor processes. SEMICON West will see a number of new developments detailed and exhibited.

Packaging Innovations Stays Focused on Flip-Chip

By Jeff Dorsch

It’s no secret that mobile devices are having a tremendous impact on the electronics and semiconductor industries. What’s less known is the impact mobile electronics is having on IC packaging, driving packaging materials manufacturers and packaging contractors to produce denser, smaller packages to fit into ever-shrinking form factors.

The inexorable drive to fit more functions on one chip, to add more chips to one package and to find cost-effective ways to package and test these chips goes on. Packaging, as a result, is taking on many more forms and types, and some packaging is shifting to the wafer level, according to industry observers and participants.

Risto Puhakka, VLSIresearchRisto Puhakka, president of market research firm VLSIresearch, says that flip-chip technology, previously confined to specialty applications, is gaining wider acceptance. “These parts of the business are going gangbusters,” he notes. “That is driven by the mobile [segment].” Packaging and test contractors are “doing well,” he adds.

Paul Lindner, executive technology director of EV Group, a supplier of bonding, lithography and nanoimprinting equipment, says the industry volumes of flip-chip packages are increasing while their costs come down. Flip-chip technology has matured, he notes, and “the trend is for smaller form factors in mobile devices,” he adds.

The wider adoption of flip chip “was predicted years ago, but every new technology takes time to develop,” Lindner says.

Also seeing “higher demand” is a newer technology, wafer-level fan-out packages, he notes.

Dan Tracy, senior director of SEMI Industry Research and Statistics, last year noted that packaging materials revenue, as a proportion of the semiconductor industry’s global revenue, has increased from about 5 percent in 2001 to an estimated 8 percent for 2012. “In the 2000s, we have seen the introduction of new form factors and configurations like stacked-die, package-on-package, wafer-level, and several other packaging types, and many of these packages require new materials and advanced substrates, thus the increase in the percentage of packaging materials revenues to semiconductor revenues,” he said.

Purveyors of semiconductor test and yield management equipment have their own perspectives on packaging innovation.

Wafer-level chip-scale packages are presenting one challenge, according to Steve Wigley, vice president of marketing for LTX-Credence. With that technology, “final test is no longer available,” he says. Companies must be satisfied with the testing proved by wafer probers, he notes.

The advent of 3DICs, while “pure memory now,” also presents a testing challenge, Wigley says. The question, he says, becomes: “How do we test this cost-effectively?” The LTX-Credence executive adds that there are “all sorts of initiatives for test standards. There’s lots of discussion, lots of debate.”

Brian Trafas, KLA-TencorBrian Trafas, chief marketing officer of KLA-Tencor, says the mobility market demands “much smaller packaging, thinner.” He adds, “These parts are driving demand.” Checking chips while they’re still on wafers is on the rise, he notes.

For KLA-Tencor and other back-end equipment companies, “being able to switch between packaging types” is highly important, Trafas says. “The flexibility is really key for the back end,” along with “high reliability,” he adds.

KLA-Tencor got deeper into the back-end equipment market with its 2008 acquisition of ICOS Vision Systems, a supplier of packaging and interconnect inspection systems, Trafas notes.

SEMICON West will have five events devoted to packaging technology, with two of them on the opening day of the show – Tuesday, July 9. At 10:30 a.m. that day, TechXPOT North in the North Hall of the Moscone Center will host “Generation Mobile: Enabled by IC Packaging Technologies.” The program will feature speakers from Advanced Semiconductor Engineering, Amkor Technology, ASE (US), Semiconductor TechInsights, SK Hynix, and Universal Scientific Industrial.

The program summary says, “Mobile electronics, with a huge spotlight on the thriving smartphone and tablet market, are fueling growth in semiconductors today, a trend expected to escalate over the years ahead. ‘Generation Mobile’ relates to consumers worldwide who now rely on such products as a way of life. As demand intensifies for higher performance, greater functionality, and lower power consumption, our industry is experiencing a strong wave of innovation, inspired by those willing to push boundaries and make these increasingly sophisticated products a reality. IC packaging has firmly established itself as a crucial part of the IC and system design process. In that vein, session speakers will discuss today’s IC packaging solutions, as well as, explore possibilities for future packaging technologies being poised to enable ‘generation mobile’ to flourish and infiltrate lifestyles around the globe.”

At 1:30 p.m. on Tuesday, July 9, the IEEE and its Components, Packaging and Manufacturing Technology Society will present a workshop at the San Francisco Marriott Marquis. The program summary for “THIN IS IN: Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era” reads, “Electronic products, such as smartphones, tablets and other consumer products, drive the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs. One of the key technologies to achieve these goals is thin 3D-packaging. Developments have lately been made with various embedding technologies, such as Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D ICs (with silicon interposers) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.”

On Thursday, July 11, at 10:30 a.m., the Advanced Packaging Committee of SEMI Americas will host “MEMS and Sensor Packaging for the Internet of Things” at TechXPOT North.

Smaller, thinner – these are the leading terms in packaging innovation these days. Cost and reliability must be part of the packaging vocabulary as well.

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By Jeff Dorsch

For all the idle talk about “the end of Moore’s Law” (always a provocative topic, and usually wrong), there’s much more shrinkage in semiconductor dimensions to achieve. However, the question of whether it’s the end of planar processes and scaling is a matter for intelligent debate.

Technologists at Intel and various research and development organizations are looking beyond the process node of 22 nanometers to what the next step will be. Intel is moving to 14 nanometers, using field-effect transistors with fins, or FinFETs, which it calls tri-gate technology. Other leading chipmakers are less ambitious, bringing out next-generation prototypes at 20nm, 18nm or 16nm.

Lode Lauwers, imecLode Lauwers, vice president of business development at imec, says his R&D and services organization is working on FinFETs and “high-mobility materials, like germanium and silicon germanium.” He adds, “We’re working on 10 nanometers, 7 nanometers.” Interconnect and barrier materials at those dimensions represent “a very big hurdle,” he notes.

“That’s where 3DIC may come in, with much shorter interconnect, Lauwers observes. One of the biggest challenges is preparing the various wafer processing steps for those nodes, especially the lithography equipment, whether it’s extreme-ultraviolet or multiple-patterning systems. “We need to take all these items together and bring them to a certain level,” he observes.

Brian Trafas, KLA-TencorBrian Trafas, KLA-Tencor’s chief marketing officer, sees a new age in processes at hand. “For foundries, at 15 or 16 nanometers, they’re introducing FinFET,” he says. “They’re going from planar to 3D. Something similar is going on in memory, NAND, 3D structures. There will be a new set of tools, 10, 14, 16 nanometer capable, across all of our product lines,” says Trafas.

At the 28-nanometer node, integrated device manufacturers and silicon foundries introduced high-k/metal gate technology, “a process stack with CMP and etch steps,” the KLA-Tencor executive observes. “That process step was very challenging.”

Indeed. Taiwan Semiconductor Manufacturing last year had significant yield issues with 28nm designs, causing some consternation among NVIDIA, Qualcomm and other TSMC customers, who could not get all of the 28nm chips they ordered.

“HKMG provided performance advantages,” Trafas says. “We saw a lot of focus on advanced bright-field inspection systems.”

For foundries, there are “still some challenges in 28-nanometer,” he adds, while adding that there are now, worldwide, some 250,000 wafer starts per month with 28nm chips.

Twenty-nanometer ICs are “not as abrupt a change; there’s more use of double-patterning lithography,” Trafas says. “This focus on shrink has been pretty challenging with 20-nanometer.” He adds that 16nm and 14nm will be “a very challenging node, because of the introduction of FinFET.”

Risto Puhakka, president of market research firm VLSIresearch says sub-22nm processes are “moving along,” yet they create “more complex optimization.” He adds, “We see people moving ahead; they’re talking 14 nanometer, 12 nanometer.”

“The big scaling benefit is moving to FinFETs,” he notes.

Paul Lindner, executive technology director at EV Group, notes that linewidth dimensions don’t matter much when it comes to back-end wafer processing. “We don’t think the end of scaling is near,” he says. “Fully depleted planar is easier to implement than tri-gate.” When it comes to sub-22nm design and manufacturing, Lindner says, “smarter system design and 3DIC integration will benefit IC technology.”

SEMICON West will address next-generation process nodes in several forums. On the opening day of the show, Tuesday, July 9, the TechXPOT South in the South Hall of the Moscone Center will hold a session on “Leveraging Nonplanar Transistor Architectures and New Materials to Power Mobility Apps Beyond 20nm.” The program summary says, The mobile market is driving the semiconductor industry to continue its move to transistor architectures that offer greater performance and power benefits than traditional planar architectures. There is not, however, only one way to achieve the required performance. IC manufacturers are pursuing different strategies including leveraging innovations in design rules. To continue the pace of development below 20nm, however, the industry will need to find suitable new channel materials and processes (e.g., MOCVD). This session will present various transistor architecture options below 20nm and the status of channel materials development. Additionally, inspection and metrology challenges associated with new materials will be discussed.”

On Thursday at 8 a.m. at the San Francisco Marriott Marquis, Entegris is holding its annual Yield Breakfast, with “Defect Reduction in the Sun-20nm Era” as its theme. The program summary reads, “The sub-20nm node is marked by skyrocketing capital expenditures, adoption of difficult process technologies such as double patterning and FinFET structure, and an ever-increasing number of process steps. Yield is not only a challenge, but a key lever to the overall semiconductor business model. In this Entegris-sponsored forum, we will explore the key yield challenges and defect reduction approaches at sub-20nm nodes from three points of view – equipment, process and materials.”

The session will include a keynote address and presentations by several industry executives, followed by a panel discussion by the speakers.

The semiconductor industry is prepared to boldly go into the sub-22-nanometer era. The technical challenges it will encounter remain to be solved.

 

Investigating Use of ‘Extreme Materials’ in Electronics

Photo Credit: Phys.orgIn 2006, when Tomás Palacios completed his PhD in electrical and computer engineering at the University of California at Santa Barbara, he was torn between taking a job in academia or industry.

“I wanted to make sure that the new ideas that we were generating could find a path toward society,” says Palacios, the newly tenured Emmanuel E. Landsman Associate Professor of Electrical Engineering and Computer Science at MIT. “In industry, I was sure that would happen; I was not sure how it would work in academia.”

“What I found when I came here,” he says, “is that MIT is really an amazing place to get all these new ideas out and to collaborate with industry to make sure that the new concepts and new ideas coming out of the university environment find their place in real products and applications.”

According to Palacios, his research group focuses on the application of what he likes to call “extreme materials” to electronics. The 25 graduate students, postdocs and  in the group are split between two major research projects: One focuses on applications of an exotic material called ; the other on applications of graphene—a form of carbon—and other “two-dimensional materials” that consist of crystals just a few atoms thick.  READ MORE

Controlling and Containing Process Variation Below 20nm

Process variation has been a major concern of IC manufacturers for many nodes now. As the industry goes below 20nm in concert with new transistor architectures and new materials for transistor channels, extending optical lithography and/or using EUVL, transitioning to 450mm wafers, more advanced wafer cleaning technologies, and so on — these multiple assaults on process variability will need to be addressed. Dr. Randhir Thakur, Executive VP and General Manager of the Silicon Systems Group at Applied Materials, discusses a three-pronged approach.

Semiconductor Industry Gets a Sharper Vision of the Future

Photo Credit: R&DThe world’s most advanced extreme-ultraviolet microscope is about to go online at the U.S. Dept. of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab), and the queue of semiconductor companies waiting to use it already stretches out the door.

The much-anticipated SHARP microscope (SEMATECH High-NA Actinic Recticle review Project) was conceived and built by scientists at Berkeley Lab’s Center for X-ray Optics (CXRO) and will provide semiconductor companies with the means to push their chip-making technology to new levels of miniaturization and complexity. The instrument is housed at the Advanced Light Source (ALS) at Berkeley Lab.

SHARP replaces an older tool, also located at the ALS, and has been many years in the making. Kenneth Goldberg, a researcher in Berkeley Lab’s Materials Sciences Div., and deputy directory of CXRO, runs the project.

“With the old tool we suffered greatly just to squeeze good results from it,” says Goldberg. “We always talked about what we’d do if we had the chance to do it right.”

Goldberg and his colleagues got that chance thanks to a partnership with SEMATECH, a consortium of semiconductor companies and chip-makers who recognized in CXRO the ideal combination of resources and expertise. Those companies are interested in developing EUV fabrication techniques in order to shrink circuit elements in their computer chips down to a few nanometers in size—five to ten times smaller than they are today.

In semiconductor fabrication, circuits of silicon are made via photolithography.    READ MORE