Process variation has been a major concern of IC manufacturers for many nodes now. As the industry goes below 20nm in concert with new transistor architectures and new materials for transistor channels, extending optical lithography and/or using EUVL, transitioning to 450mm wafers, more advanced wafer cleaning technologies, and so on — these multiple assaults on process variability will need to be addressed. Dr. Randhir Thakur, Executive VP and General Manager of the Silicon Systems Group at Applied Materials, discusses a three-pronged approach.
MySemiconDailyTV interviewed Dan Armbrust, President & CEO of SEMATECH in advance of SEMICON West 2013, where he will be a presenter at the R&D Panel: “A conversation on the future of semiconductor manufacturing” (Wednesday July 10 from 10:00AM-11:00AM). Because the semiconductor industry faces a growing chorus of competing interests and economic realities, i.e., near parallel introductions of new transistor architectures, new channel materials, optical lithography extensions and EUV lithography, 450mm wafers, and stacked 3D ICs, it has to find more efficient ways to accomplish R&D. “It would certainly be convenient if we could narrow our focus to fewer of the things we need to do,” Armbrust told MSDTV. “Unfortunately, we need to do them all.” The necessity, he explains, is driven by customer expectations for continued advancements in power, performance, and lower cost. “As an industry, if we’re going to stay on the growth curve we’ve been on and remain vital, we’re going to have to solve all of the problems.”
The challenges facing the industry have a common denominator — they are difficult, complex, and have a fair amount of uncertainty, both technical and economic. “We need to respond to that uncertainty challenge by coordinating better across the entire industry,” said Armbrust. “And that means, wherever possible, reducing redundancies and eliminating waste.” He also pointed out that the timing has to be correct, i.e., when each challenge is addressed, how solutions are introduced, and getting to volume manufacturing much faster than in the past.
With the price points of consumer electronics — especially mobile devices — continuing to be under pressure, semiconductor manufacturers will continue to be challenged with leveraging their participation in R&D consortia ever more efficiently. And consortia will have to adapt accordingly. What doesn’t change is that, as usual, consortia will be working to bring the industry to a consensus and prioritizing actions, as well as identifying infrastructure gaps and addressing them. “The entire supply chain is under pressure to continuously adapt – and to prepare the technology with much more significant up front investment,” said Armbrust. The “why” gets back to uncertainty he pointed out. “If you look at the device roadmap — there’s significant questions about what happens — what’s the next big step as we get closer to the end of scaling as we’re used to it. Similarly, when each new technology will be introduced has a fair amount of uncertainty around it and a lot of people in the industry are talking about how the changes should be sequenced, and the interaction between them.” The degree of technical uncertainty is compounded by the economic uncertainty, i.e., can the changes be introduced while continuing to drive down costs.
To help deal with the uncertainty, Armbrust suggests the industry can get some inspiration from its roots. After all, in the beginning, the semiconductor industry was a bunch of start-ups that had restrictions on resources and were under constant time pressure. SEMATECH has been looking at what start-ups are doing today and applying the lessons learned to the dynamic semiconductor industry environment. “If we’re quick on our feet, we’ll be able to pick the right problems, and work on them when they matter, and pull the industry together in a way that makes sense…quickness and speed will matter.”
Photo Credit: Solid State TechnologyThis year’s SEMICON West front-end processing TechXPOTs on lithography and transistors below 20nm will provide critical updates on how technologists are coping with the next scaling challenges. This article is based on commentary on extending optical lithography and the outlook for DSA from TechXPOT speakers.
It’s no secret that the industry is still waiting for EUV lithography’s full potential to be realized and that the continued extension of optical lithography, specifically 193 immersion lithography, has enabled the industry to keep scaling. As ArF capabilities are extended, sophisticated illumination systems will be crucial in order to satisfy aggressive CD requirements, Stephen Renwick, senior research scientist at Nikon Research Corporation of America, told SEMI.
“Computational lithography solutions that maximize process windows, provide robust OPC strategies across tools, as well as the means to compensate for lens and thermal aberrations become increasingly vital,” said Renwick, who will present at SEMICON West on July 10.
Nikon’s latest iteration of its immersion scanner, the Streamlign Platform, enables mix-and-match overlay (MMO) accuracy ≤3.5nm to satisfy the stringent requirements for advanced multiple patterning applications sub-20nm. Renwick also explained that stable overlay performance under different exposure conditions is imperative for high-volume manufacturing. Figure 1 shows the critical layer requirements beyond 20nm with respect to mix-and-match overlay and focus accuracy. Renwick’s TechXPOT presentation will cover a number of advanced overlay control solutions that aid in grid matching/stabilization control, compensate for reticle deformation, and provide overlay analysis/optimization capabilities. READ MORE
by Debra Vogler, Instant Insight Inc., Sunnyvale, CA
In a column written before SEMICON West 2012, SEMICON West: Spectator or Participant?, I promised to share some data about the news and events surrounding the show culled from social media traffic. Tradeshow Media Partners – the folks who brought you the Show Dailies during West – measured the number of people, companies, and entities that engaged in immediate and extended content and conversations (related to the show) over a 10-day period of time. The results are in and – of course – engineers rule!
A total of 13.4 million social impressions (i.e., tweets, postings, conversations) across Twitter, Google+, LinkedIn, and Facebook, were generated by a total of 11,230 global contributors. These global contributors broke down into the following categories: 41.2% were engineers, 21.9% were researchers and/or analysts, 18.5% were in marketing and sales; at the bottom were industry executives (6.1%) and designers (3.9%).
While it is expected that the greatest percentage of the 11,230 participants (27.3%) would come from the U.S., the rest of the participants in social media directly related to the show settled out as follows: 11.4% from South Korea, 11.1% from Taiwan, 9.8% from China, and 8.9% from the Netherlands. Other countries contributed percentages below 8%.
Of the more than 400 terms, product categories, and interest areas that were tracked, it might be somewhat surprising that materials was the highest trending topic (at 43.5%) with wafer processing coming in at 40.2%. All other categories were less than 40% (though test/devices almost made it at 39.8%). Within the topic of packaging (at 33.7%), the number one trending topic was 3D ICs with fine-pitch interconnects coming in second.
I’m not a marketer and I don’t play one on TV, but if I had to guess, I’d say the enthusiasm with which engineers contributed to the discussion about SEMICON West on social media platforms is probably a reflection of the intense efforts currently occurring to develop the solutions needed for sub-22nm equipment and materials sets – whether for 3D ICs, new transistor architectures, or lithography. Someone has to choose all those new components, materials, and design elements to make sub-22nm processes and platforms a reality. So if someone says engineers aren’t social, don’t believe them!
