By Jeff Dorsch

Everybody loves FinFETs!

Well, not everybody, really, is behind double-gate or multiple-gate field-effect transistors. There is a camp in the semiconductor industry making the case for the leading alternative, using fully-depleted silicon-on-insulator technology. On balance, however, most chipmakers are betting on the chips with the tiny “fins.”

There’s also some disagreement and fudging on what is and isn’t a FinFET process. It’s not a precisely defined term for many people. Intel, for instance, was a leader in implementing the architecture, but it doesn’t use the word “FinFET,” preferring to describe its architecture as a “3-D Tri-Gate transistor.”

Intel started using the Tri-Gate architecture at the 22-nanometer process node and now is employing it at 14nm.

Taiwan Semiconductor Manufacturing, the world’s largest pure-play silicon foundry, is using FinFETs at the 16nm process node. The foundry has introduced its 16nm FF+ process, a second-generation FinFET technology.

“Most of the major manufacturers are doing FinFETs,” says Aaron Thean, vice president of process technology and director of logic development at imec. “Everyone is transitioning to FinFETs. The industry is moving in that direction.”

Brian Trafas, chief marketing officer of KLA-Tencor, says, “Most companies chose FinFET.” With his company’s emphasis on process control and yield management, KLA-Tencor knows about some of the struggles in implementing FinFET architectures. There is some residual contamination with the etching and cleaning process steps, according to Trafas. This often takes the form of “very small residue on the sidewall of fins,” he says.

What about fully-depleted silicon-on-insulator? “FD-SOI can help with some of the scaling,” Trafas says. It is, however, what he describes as “a niche area.”

STMicroelectronics has been the industry champion of FD-SOI technology, and that’s been a lonely position, for the most part, although it continues to collaborate with CEA-Leti and Soitec on implementing the technology. GlobalFoundries committed to using ST’s FD-SOI tech for 28nm and 20nm production in 2012, and expects to put it into volume production by the end of this year, for 28nm and 14nm processes.

In May, STMicroelectronics announced that Samsung Electronics would use ST’s 28nm FD-SOI tech for foundry customers. Samsung plans to offer the process in early 2015.

“The agreement [for 28nm FD-SOI] confirms and strengthens further the business momentum that we have experienced on this technology during the past quarters through many customers and project engagements in our embedded processing solutions segment,” ST Chief Operating Officer Jean-Marc Chery said in a press statement. “We foresee further expansion of the 28nm FD-SOI ecosystem, to include the leading EDA and IP suppliers, which will enrich the IP catalog available for 28nm FD-SOI.”

Meanwhile, process technologists are planning for FinFETs at 10nm, 7nm, and 5nm. Beyond that, it’s anyone’s guess what architecture will prevail.

By Jeff Dorsch

Extreme-ultraviolet lithography is making progress!

Well, check that. EUV technology is progressing, yet it remains uncertain when its insertion into volume production of semiconductors will occur.

ASML Holding doesn’t want to discuss publicly the wattage of its Cymer power sources for the NXE:3300 EUV scanner.  Ryan Young of ASML says there are two main elements to the company’s EUV tools – power and availability. With the latter, “we’re talking about wafers through the machine, which is what customers are interested in,” he says.

The 3300 is now capable of producing 100 wafers per day, and ASML is working to bring that up to 500 wafers a day, according to Young. ASML’s goal is to have the scanner turning out 70 wafers per hour by the end of 2014, with an eye toward a goal of 125 wafers per hour in 2015. “We’re continuing to drive productivity for our customers,” Young says.

Getting to 70 wph by the end of this year is a “significant improvement” for the 3300, he adds.

Whether EUV is inserted at the 10-nanometer process node or the 7nm node is “highly customer-dependent,” Young notes.

Kurt Ronse, program director of advanced lithography at imec, is less recalcitrant to talk about the 3300 power source’s wattage. He says the sources at ASML facilities and at customer installations in the field have achieved 40 watts to 60 watts of power output, and some have gotten up to 70 watts. “We are not at 250 watts yet,” Ronse says, the level widely believed to be necessary for chip production in volume.

For the 3300s in the field, “uptime has improved since SPIE,” the Advanced Lithography conference in late February, the imec executive says. At 40W-60W, “this has to increase,” Ronse notes, with 250W a possibility in 2015. “We are not there yet, but it is very encouraging,” he says.

Progress is also being made in the areas of reticles and resists, according to Ronse. For resists, there are “steady improvements from year to year,” he says. Still, “improvements are relatively slow,” he adds. Ronse says there are issues with line-edge roughness that are being addressed by resist manufacturers, university researchers, and small chemical companies.

Still, the power source is a major concern for lithography scientists, according to Ronse. Progress in that area is “always slower than people are predicting,” he says.

For now, the semiconductor industry is dealing with 193nm immersion lithography, with its double patterning and multiple patterning. Ronse calls immersion lithography “extremely expensive, extremely slow, and hard to justify economically.” The industry is now hoping for EUV’s insertion, with a return to one-pass patterning, at the 7nm process node, he says.

ASML’s Young notes that a full-size pellicle has been developed for EUV reticles, an important step forward. ASML has fully qualified and shipped six NXE-3300B systems to customers, and five more are in the process of integration, he says.

For all the attention paid to ASML’s EUV program, the company remains a significant supplier of deep-ultraviolet scanners. The company this week is touting its “Million Wafer Club” – the 350 DUV scanners in the field that achieved the output of 1 million wafers per year, Young notes. One new scanner in particular has processed 1.5 million wafers in 12 months, he says. That works out to about 4,000 wafers a day (one scanner pumped out 5,250 wafers in one day, or nearly 219 wafers per hour).

Young also touts ASML’s Brion Technologies division, which specializes in software complementing the company’s scanners in the areas of computational lithography, optical proximity correction, resolution enhancement technology, and source mask optimization. Brion’s software is “keeping the process as tight as possible,” Young says.

In conclusion, the word on extreme-ultraviolet lithography is pretty much the same as it was a year ago: It’s coming, but it’s not here yet.

By Jeff Dorsch

Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing have made their moves into three-dimensional semiconductors. Now it remains to be seen how the rest of the semiconductor industry will make the transition to 3DICs.

It’s not going to be another dimension shrink, by any means. As difficult as the transition to fabrication with 28-nanometer features was for many chipmakers (and remains so for many second-tier semiconductor manufacturers), that scaling shift will seem like child’s play as integrated device manufacturers and silicon foundries deal with silicon interposers, through-silicon vias, and other accoutrements of the 3D chip world.

Yole Développement estimates the value of semiconductors with TSVs in 3DIC and 3D wafer-level chip-scale packages – including ambient light sensors, CMOS image sensors, power amplifiers, and inertial and radio-frequency microelectromechanical system devices – was $2.7 billion in 2012. It forecasts that such chips will represent 9 percent of the semiconductor market in 2017, with nearly $40 billion in value.

Transparency Market Research has a more modest forecast for 3DICs. It estimates the value of 3D chips in 2012 was $2.4 billion and will rise at a compound annual growth rate of 18.1 percent over the next five years, hitting $7.52 billion in 2019.

“Customers like to scale their devices for greater performance or better battery life,” says Brian Trafas, chief marketing officer of KLA-Tencor. “They’re moving from 2D to 3D.”

“The logic leader” (generally known as Intel) made its move at the 22-nanometer process node, Trafas notes, while “the foundry leader” (that would be TSMC) migrated to 3D at 16nm, Trafas notes. In advanced 3D memory chips, “one leader is out front,” he says, announcing that its wafer fabrication facility in China is producing 3D NAND flash memories (that’s Samsung).

As the technology leaders enter the brave new world of 3D chips, “we do now see some spending for 14- and 16-nanometer by foundries,” Trafas says.

Making 3DICs calls for multiple patterning in photolithography and “more process steps,” the KLA-Tencor executive says, which is good for sales of process control equipment. “The logic leader” experienced yield issues when it started making 3D chips, and “we’re seeing the same thing with foundries,” Trafas says. “It’s very challenging.

“It’s somewhat like 28-nanometer. It’s typical of what you see at all new nodes,” he adds.

Despite the challenges in defects and yield with 3DICs, “it should be successful,” Trafas concludes.

At SEMICON West, 3DICs will be under discussion in several forums, including the TechXPOT programs in Moscone Center’s North and South halls.

Like it or not, 3DICs are here. Better brush up on those TSVs.

A collection of the first fully patterned 450mm wafers are on display at SEMICON West this week at the newly merged SUNY CNSE/SUNYIT exhibit, booth 517, located in the Moscone Center’s South Hall. The wafers will be on display throughout the exhibition and showcased in the 450 mm Technology Development Session on Thursday July 10^th.

Fully patterned 450mm wafers have been shown before, most notably those produced using Molecular Imprints’ Imprio nanoimprint lithography (NIL) tool. At SEMI’s ISS meeting in Jaunary 2013, Intel’s Bob Bruck famously held such a wafer before the crowd.

But the 450mm wafers on display this week were produced using Nikon’s 193 immersion scanner, making it the first of its kind using conventional lithography tools now in use for 300mm wafer production.

“These first 450mm wafers are tangible proof that the industry’s transition to this next generation technology is on track and gaining momentum,” said Paul Farrar, Jr., Vice President for Manufacturing Innovation of the newly merged SUNY CNSE/SUNYIT institution and General Manager of the G450C.

The Nikon immersion scanner will join existing 450mm infrastructure at the Albany NanoTech Complex in April of 2015 in accordance with the project timeline.  This critical milestone will enable G450C founding members and CNSE to perform 10nm and below, full wafer photolithography, while optimizing tool configuration and performance.

In July of 2013, New York’s Governor Cuomo announced a $350 million partnership between the newly merged CNSE/SUNYIT and Nikon to develop next generation 450mm photolithography technology. Nikon and the newly merged CNSE/SUNYIT brought about a first of its kind immersion lithography scanner online in less than 12 months, enabling the vital wafer exposures that will further advance the industry’s transition from the current 300mm wafer platform to the next generation 450mm wafer platform.  The wafers that presented at SEMICON West are the first produced in support of the G450C, a public-private partnership headquartered at the NanoTech complex in Albany, NY.

“Nikon is very pleased to have achieved this key milestone, and we are intent on beginning the next phase of this program, said Nikon Corporation Senior Vice President and Semiconductor Lithography Business Unit General Manager, Toshikazu Umatate. “450mm scanner development is progressing on target to deliver the performance and productivity innovations that will deliver reduced cost per die, which is essential for the continuation of Moore’s Law.”

To date, more than $350 million in 450mm wafer tools have been installed at the Albany NanoTech Complex.  With the arrival of the Nikon immersion photolithography tool, the investment will swell to over $700 million.

One the first fully patterned 450mm wafers produced using conventional 193 immersion lithography.

By Jeff Dorsch

The long night in solar energy may be coming to an end.

The comeback from the doldrums of 2011-13 could be told in the stock price of SolarCity, an installer of solar panels for business, government, and homes. Since falling to about $10 a share in early 2013, SCTY shares hit a peak of more than $88 in March. After tailing off this spring, SolarCity’s stock has rebounded in recent weeks, closing on July 1 at $71.22 a share.

Semiconductor Equipment and Materials International last month reported that global bookings for photovoltaic manufacturing equipment were $296 million for the first quarter of 2014, a 44 percent gain from a year earlier. Q1 worldwide billings were $240 million, down 6 percent from the first quarter of 2013, SEMI said, resulting in a quarterly book-to-bill ratio of 1.24 – the first time that ratio has been above parity in three years.

PV equipment makers had to struggle through 2013 before seeing business pick up this year. The book-to-bill ratio for the fourth quarter of last year was 0.61. For all of 2013, billings totaled $1.22 billion, off by 49 percent from 2012’s $2.40 billion, while bookings were $736 million, down 17 percent from the previous year’s $883 million, according to SEMI. Customers in Asia represented 78% of 2013 billings.

The Intersolar North America conference and exhibition will run this week in conjunction with SEMICON West. The conference is scheduled for July 7-9 at the InterContinental Hotel, while the exhibition is July 8-10 at Moscone West.

The U.S. solar market saw 4.2 gigawatts installed last year, and the forecast for 2014 is that American solar power capacity will grow by 5.2 gigawatts to 6.3 gigawatts, according to NPD SolarBuzz.

Belgium’s imec continues to work on thin-film solar cells and silicon-based solar cells. Most of the latter are p-type silicon, but there is a shift toward n-type silicon in solar cells now, according to Philip Pieters, imec’s business development director. These n-type silicon solar cells are capable of an energy-conversion efficiency rate of 21.5 percent, a figure certified by Germany’s Fraunhofer ISE-CalLab. Meco Equipment Engineers worked with imec on the nickel/copper plating for the front contacts on the solar cells, which were fabricated on square substrates measuring 156 millimeters by 156mm.

These processes could be “easily updated” for industry’s use in volume production of silicon-based solar cells, Pieters said.

The Intersolar North America conference will have multiple sessions on photovoltaics, energy storage, and solar heating and cooling on all three days, along with workshops and special events.

Sunny prospects await photovoltaics in 2014, it is clear.

By Jeff Dorsch

With mobile devices continuing to shrink in size and wearable electronics emerging as a new market for semiconductors, advanced packaging technologies are taking on increasing importance in the global supply chain. Aside from the 3DIC package/system-in-package area, what is going on in semiconductor packaging these days?

Flip-chip and wafer-level packaging, among other types of chip-scale packaging (CSP), are progressing in technology development and industry adoption. They are not new technologies, but the multiple types of CSPs continue to proliferate.

Wafer-level chip-scale packaging (WLCSP) is being employed in the iPhone and other mobile devices. TechSearch International forecasts that the number of devices in wafer-level packages will more than double over seven years, reaching nearly 36.8 billion devices in 2017.

STATS ChipPAC, one the world’s largest contractors in IC assembly and testing services, recently introduced an encapsulated wafer-level chip-scale package, which it says can help prevent damage to the chip during the surface-mounting process.

“WLCSP is a bare-die package that is constantly exposed to potential cracking, chipping and handling damages before or during the SMT process. This is particularly true for advanced node products where the die is very thin and dielectric layers are extremely fragile,” Dr. Han Byung Joon, executive vice president and chief technology officer of STATS ChipPAC, said in a statement. “As mobile device manufacturers tighten their technical specifications to reach new levels of reliability in their products, the industry will see more stringent component level and board-level reliability (BLR) requirements. eWLCSPTM is a robust packaging solution that cost-effectively addresses the increased durability requirements for our customers in advanced silicon nodes down to 28nm.”

Amkor Technology, another large provider of chip assembly and test services, has seen the percentage of its revenue from advanced products (including flip chip, wafer-level processing and related test services) increase from 40.5 percent in 2011 to 49.1 percent in 2013. The company offers three options in WLCSP — CSPnl bump on repassivation, CSPnl bump on redistribution, and CSPn3. These packages can have from four to 196 solder balls.

Advanced Semiconductor Engineering, another of the Big 4 in IC assembly and test services, offers a number of advanced packaging types, such as WLCSP, flip-chip CSP, flip-chip package-in-package, flip-chip ball grid array and its Advanced Single Sided Substrate, trademarked as aS 3. These types can accommodate from six to 2,916 leads.

In 2013, ASE saw its percentage of packaging revenue from advanced packaging increase to 26.7 percent from 2012’s 23.6 percent.

There are many other types of advanced packages, including ball grid arrays (BGAs), bump chip carriers (BCCs), and thin quad flat packages (TQFPs). BGAs have a host of variations, such as flip-chip BGAs and thin BGAs. (Packaging is a big bowl of alphabet soup with all its acronyms – that’s another article.) Intel has been using BGA packages since the days of the Pentium II microprocessors and the first Celeron mobile processors. It currently employs a “Micro-FCBGA” package for its mobile processors, containing 479 solder balls.

Land grid arrays, which Intel is making greater use of in the last five years, are basically a BGA without the solder balls.

Bump chip carriers are used in cell phones, digital cameras, wireless local-area networks, and other products.

Amkor touts its thin quad flat packs for application-specific integrated circuits, controllers, digital signal processors, field-programmable gate arrays, PC chipsets, processors, programmable logic devices, and static random-access memories. There are a wide variety of quad flat package types.

Dynamic random-access memories get their own advanced packaging, too. Fine-pitch BGAs are used for high-speed DRAMs.

Technical sessions on advanced packaging will be featured on the first two days of SEMICON West. Tuesday, July 8, will see “Mobility and More – The M&Ms of Cost Beneficial Advanced Packaging” in the morning and “Embracing What’s NEXT – Devices & Systems for Big Data, Cloud and IoT” in the afternoon. (You may have heard of the Internet of Things, or IoT, by now.) The afternoon of Wednesday, July 9, will have “Driving Automotive Innovation – The Enabling Role of Semiconductor and IC Packaging.”

As always, it should be another interesting year in advanced packaging!

SEMI today announced that Martin Anstice, president and CEO, Lam Research Corporation; Kevin Crofton, president and COO, SPTS Technologies; Tien Wu, COO, ASE Group; and Guoming Zhang, executive vice president, Sevenstar Electronics, were elected as new directors to the SEMI International Board of Directors in accordance with the association’s by-laws.

Six current board members were re-elected for a two-year term:  Nobu Koshiba, president and representative director, JSR Corporation; Yong Han Lee, chairman, Wonik; Sue Lin, vice chairman, Hermes Epitek; Toshio Maruyama, chairman, Advantest Corporation; Tetsuo Tsuneishi, vice-chairman of the board, Tokyo Electron, Ltd.; Natsunosuke Yago, president and representative director, chairman of the board, Ebara Corporation.

Additionally, the SEMI Executive Committee confirmed the continued leadership by André-Jacques Auberton-Hervé, chairman, CEO and president of Soitec, as SEMI chairman and Yong Han Lee, chairman of Wonik, as SEMI vice-chairman.

The leadership appointments and elected board members’ tenure becomes effective at the annual SEMI membership meeting, to be held Wednesday, July 9, during the SEMICON West 2014 exposition in San Francisco, California.

“We are honored to have four distinguished industry leaders joining the SEMI Board and appreciate the continued service of those that have been reelected,” said Denny McGuirk, president and CEO of SEMI. “The SEMI Board reflects the regional and market diversity of our worldwide membership. Their service, commitment and leadership are tremendous assets for our association and our industry.”

SEMI’s 20 voting directors and 11 emeritus directors represent companies from Europe, China, Japan, Korea, North America, and Taiwan, reflecting the global scope of the association’s activities. SEMI directors are elected by the general membership as voting members of the board and can serve a total of five two-year terms.

SEMI projects back-to-back years of double-digit growth in worldwide semiconductor equipment sales according to the mid-year edition of the SEMI Capital Equipment Forecast, released here today at the annual SEMICON West exposition. The SEMI outlook calls for the total semiconductor equipment market to grow 20.8 percent in 2014 to reach $38.4 billion and to expand another 10.8 percent in 2015 to exceed $42.6 billion.

Following two years of spending declines, key drivers for equipment spending are investments by foundry and logic fabs for sub 20nm technology, NAND flash makers for leading edge technology (including 3D NAND) and capacity, DRAM technology upgrades for mobile applications, and expansion of advanced packaging capacity for flip chip, wafer bumping, and wafer-level packaging.  All regions of the world are projected to see equipment spending increases in 2015.  Front-end wafer processing equipment is forecast to grow 11.9 percent in 2015 to $34.8 billion, up from $31.1 billion in 2014.  Test equipment and assembly and packaging equipment is forecast to experience growth next year, rising to $3.1 billion (+1.6 percent) and $2.6 billion (+1.2 percent), respectively. The forecast indicates that next year is on track to be the second largest spending year ever, surpassed only by $47.7 billion spent in 2000.

“Mobility and interconnectivity require leading–edge process technologies, both at the fab level and in packaging, and are key factors for growth in equipment spending,” said Denny McGuirk, president and CEO of SEMI. “We expect capital spending to increase throughout the remainder of 2014 and into 2015.”

Growth is forecast in all regions except ROW in 2014 and all regions in 2015. Taiwan is forecast to continue to be the world’s largest spender with $11.6 billion estimated for 2014 and $12.3 billion for 2015. In 2014, North America is second at $7.2 billion, followed by South Korea at $6.9 billion. For 2015, South Korea is in second ($8.0 billion) in spending, followed by North America ($7.3 billion).

In 2014, year-over-year increases are expected to be largest for China (47.3 percent), North America (35.7 percent), South Korea (33.0 percent), and Europe (29.7 percent). Year-over-year percentage increases for 2015 are largest for Europe (47.8 percent increase), ROW (23.5 percent), Japan (15.6 percent), and South Korea (15.0 percent).

The following results are given in terms of market size in billions of U.S. dollars and percentage growth over the prior year:

SEMI 2014 Mid-Year Equipment Forecast by Market Region

Source: SEMI, July 2014; Equipment Market Data Subscription (EMDS)