By Shannon Davis, Web Editor, Solid State Technology

Micron President Mark Adams’ keynote on Tuesday morning at SEMICON West 2014 was both optimistic and challenging, perhaps even unsettling for companies unused to evolving with the times.

“This is a great time for technology! And it’s just beginning…the pace of innovation is accelerating; we haven’t reached our peak,” said Mr. Adams. “The role of computing, automation, intelligence, storage is going to just grow and grow.”

But this boom in growth is not without its unique and significant challenges, and those not preparing for the change now may not be here to change later, he warned.

“For companies thinking everything’s going to stay the same, they’re not going to make it. You have to be able to adapt,” Mr. Adams challenged his audience. “We need to adapt to what’s in front of us. There are new markets and new applications. How we design our products and run our factories has to change, too.”

This call to evolve wasn’t reserved solely for the semiconductor makers, either. Mr. Adams pointed to the equipment suppliers as well, who he said would also need to work closer with their customers to learn how to meet their needs, relying less on the roadmap and more on real engagement with their partners.

“The key is the partnership aspect – running a semiconductor company is getting tougher,” said Mr. Adams. “We need partnerships. Semiconductor companies need equipment companies more than ever.”

But given the dynamics that are going on in the market currently, a successful partnership is different, he said. The partnerships of today, he explained, would need to be more solutions-oriented and less cost-focused.

Mr. Adams proposed engaging customers to understand market requirements and solve customer problems – a challenging proposal, given the now-diverse markets the semiconductor industry serves.

“For those companies who are structured, investing and partnering to understand how to best serve these markets, these are the winners,” said Mr. Adams. “We need to enable their solutions. We need to move up the value chain and add value to the products we’re selling.”

Mr. Adams concluded by outlining five factors that could make or break evolving semiconductor partnering companies: their ability to engage in safety analysis, their speed to market and cycle times, the quality of the products they deliver, their time to mature yield, and their ability to provide cost-effective options for their services.

“There is a huge opportunity in front of us,” he concluded. “We can only capitalize on it if we partner together more closely than we ever have before.”

Photo provided by SEMI

By Jeff Dorsch

Everybody loves FinFETs!

Well, not everybody, really, is behind double-gate or multiple-gate field-effect transistors. There is a camp in the semiconductor industry making the case for the leading alternative, using fully-depleted silicon-on-insulator technology. On balance, however, most chipmakers are betting on the chips with the tiny “fins.”

There’s also some disagreement and fudging on what is and isn’t a FinFET process. It’s not a precisely defined term for many people. Intel, for instance, was a leader in implementing the architecture, but it doesn’t use the word “FinFET,” preferring to describe its architecture as a “3-D Tri-Gate transistor.”

Intel started using the Tri-Gate architecture at the 22-nanometer process node and now is employing it at 14nm.

Taiwan Semiconductor Manufacturing, the world’s largest pure-play silicon foundry, is using FinFETs at the 16nm process node. The foundry has introduced its 16nm FF+ process, a second-generation FinFET technology.

“Most of the major manufacturers are doing FinFETs,” says Aaron Thean, vice president of process technology and director of logic development at imec. “Everyone is transitioning to FinFETs. The industry is moving in that direction.”

Brian Trafas, chief marketing officer of KLA-Tencor, says, “Most companies chose FinFET.” With his company’s emphasis on process control and yield management, KLA-Tencor knows about some of the struggles in implementing FinFET architectures. There is some residual contamination with the etching and cleaning process steps, according to Trafas. This often takes the form of “very small residue on the sidewall of fins,” he says.

What about fully-depleted silicon-on-insulator? “FD-SOI can help with some of the scaling,” Trafas says. It is, however, what he describes as “a niche area.”

STMicroelectronics has been the industry champion of FD-SOI technology, and that’s been a lonely position, for the most part, although it continues to collaborate with CEA-Leti and Soitec on implementing the technology. GlobalFoundries committed to using ST’s FD-SOI tech for 28nm and 20nm production in 2012, and expects to put it into volume production by the end of this year, for 28nm and 14nm processes.

In May, STMicroelectronics announced that Samsung Electronics would use ST’s 28nm FD-SOI tech for foundry customers. Samsung plans to offer the process in early 2015.

“The agreement [for 28nm FD-SOI] confirms and strengthens further the business momentum that we have experienced on this technology during the past quarters through many customers and project engagements in our embedded processing solutions segment,” ST Chief Operating Officer Jean-Marc Chery said in a press statement. “We foresee further expansion of the 28nm FD-SOI ecosystem, to include the leading EDA and IP suppliers, which will enrich the IP catalog available for 28nm FD-SOI.”

Meanwhile, process technologists are planning for FinFETs at 10nm, 7nm, and 5nm. Beyond that, it’s anyone’s guess what architecture will prevail.

By Jeff Dorsch

Extreme-ultraviolet lithography is making progress!

Well, check that. EUV technology is progressing, yet it remains uncertain when its insertion into volume production of semiconductors will occur.

ASML Holding doesn’t want to discuss publicly the wattage of its Cymer power sources for the NXE:3300 EUV scanner.  Ryan Young of ASML says there are two main elements to the company’s EUV tools – power and availability. With the latter, “we’re talking about wafers through the machine, which is what customers are interested in,” he says.

The 3300 is now capable of producing 100 wafers per day, and ASML is working to bring that up to 500 wafers a day, according to Young. ASML’s goal is to have the scanner turning out 70 wafers per hour by the end of 2014, with an eye toward a goal of 125 wafers per hour in 2015. “We’re continuing to drive productivity for our customers,” Young says.

Getting to 70 wph by the end of this year is a “significant improvement” for the 3300, he adds.

Whether EUV is inserted at the 10-nanometer process node or the 7nm node is “highly customer-dependent,” Young notes.

Kurt Ronse, program director of advanced lithography at imec, is less recalcitrant to talk about the 3300 power source’s wattage. He says the sources at ASML facilities and at customer installations in the field have achieved 40 watts to 60 watts of power output, and some have gotten up to 70 watts. “We are not at 250 watts yet,” Ronse says, the level widely believed to be necessary for chip production in volume.

For the 3300s in the field, “uptime has improved since SPIE,” the Advanced Lithography conference in late February, the imec executive says. At 40W-60W, “this has to increase,” Ronse notes, with 250W a possibility in 2015. “We are not there yet, but it is very encouraging,” he says.

Progress is also being made in the areas of reticles and resists, according to Ronse. For resists, there are “steady improvements from year to year,” he says. Still, “improvements are relatively slow,” he adds. Ronse says there are issues with line-edge roughness that are being addressed by resist manufacturers, university researchers, and small chemical companies.

Still, the power source is a major concern for lithography scientists, according to Ronse. Progress in that area is “always slower than people are predicting,” he says.

For now, the semiconductor industry is dealing with 193nm immersion lithography, with its double patterning and multiple patterning. Ronse calls immersion lithography “extremely expensive, extremely slow, and hard to justify economically.” The industry is now hoping for EUV’s insertion, with a return to one-pass patterning, at the 7nm process node, he says.

ASML’s Young notes that a full-size pellicle has been developed for EUV reticles, an important step forward. ASML has fully qualified and shipped six NXE-3300B systems to customers, and five more are in the process of integration, he says.

For all the attention paid to ASML’s EUV program, the company remains a significant supplier of deep-ultraviolet scanners. The company this week is touting its “Million Wafer Club” – the 350 DUV scanners in the field that achieved the output of 1 million wafers per year, Young notes. One new scanner in particular has processed 1.5 million wafers in 12 months, he says. That works out to about 4,000 wafers a day (one scanner pumped out 5,250 wafers in one day, or nearly 219 wafers per hour).

Young also touts ASML’s Brion Technologies division, which specializes in software complementing the company’s scanners in the areas of computational lithography, optical proximity correction, resolution enhancement technology, and source mask optimization. Brion’s software is “keeping the process as tight as possible,” Young says.

In conclusion, the word on extreme-ultraviolet lithography is pretty much the same as it was a year ago: It’s coming, but it’s not here yet.

By Jeff Dorsch

Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing have made their moves into three-dimensional semiconductors. Now it remains to be seen how the rest of the semiconductor industry will make the transition to 3DICs.

It’s not going to be another dimension shrink, by any means. As difficult as the transition to fabrication with 28-nanometer features was for many chipmakers (and remains so for many second-tier semiconductor manufacturers), that scaling shift will seem like child’s play as integrated device manufacturers and silicon foundries deal with silicon interposers, through-silicon vias, and other accoutrements of the 3D chip world.

Yole Développement estimates the value of semiconductors with TSVs in 3DIC and 3D wafer-level chip-scale packages – including ambient light sensors, CMOS image sensors, power amplifiers, and inertial and radio-frequency microelectromechanical system devices – was $2.7 billion in 2012. It forecasts that such chips will represent 9 percent of the semiconductor market in 2017, with nearly $40 billion in value.

Transparency Market Research has a more modest forecast for 3DICs. It estimates the value of 3D chips in 2012 was $2.4 billion and will rise at a compound annual growth rate of 18.1 percent over the next five years, hitting $7.52 billion in 2019.

“Customers like to scale their devices for greater performance or better battery life,” says Brian Trafas, chief marketing officer of KLA-Tencor. “They’re moving from 2D to 3D.”

“The logic leader” (generally known as Intel) made its move at the 22-nanometer process node, Trafas notes, while “the foundry leader” (that would be TSMC) migrated to 3D at 16nm, Trafas notes. In advanced 3D memory chips, “one leader is out front,” he says, announcing that its wafer fabrication facility in China is producing 3D NAND flash memories (that’s Samsung).

As the technology leaders enter the brave new world of 3D chips, “we do now see some spending for 14- and 16-nanometer by foundries,” Trafas says.

Making 3DICs calls for multiple patterning in photolithography and “more process steps,” the KLA-Tencor executive says, which is good for sales of process control equipment. “The logic leader” experienced yield issues when it started making 3D chips, and “we’re seeing the same thing with foundries,” Trafas says. “It’s very challenging.

“It’s somewhat like 28-nanometer. It’s typical of what you see at all new nodes,” he adds.

Despite the challenges in defects and yield with 3DICs, “it should be successful,” Trafas concludes.

At SEMICON West, 3DICs will be under discussion in several forums, including the TechXPOT programs in Moscone Center’s North and South halls.

Like it or not, 3DICs are here. Better brush up on those TSVs.

A collection of the first fully patterned 450mm wafers are on display at SEMICON West this week at the newly merged SUNY CNSE/SUNYIT exhibit, booth 517, located in the Moscone Center’s South Hall. The wafers will be on display throughout the exhibition and showcased in the 450 mm Technology Development Session on Thursday July 10^th.

Fully patterned 450mm wafers have been shown before, most notably those produced using Molecular Imprints’ Imprio nanoimprint lithography (NIL) tool. At SEMI’s ISS meeting in Jaunary 2013, Intel’s Bob Bruck famously held such a wafer before the crowd.

But the 450mm wafers on display this week were produced using Nikon’s 193 immersion scanner, making it the first of its kind using conventional lithography tools now in use for 300mm wafer production.

“These first 450mm wafers are tangible proof that the industry’s transition to this next generation technology is on track and gaining momentum,” said Paul Farrar, Jr., Vice President for Manufacturing Innovation of the newly merged SUNY CNSE/SUNYIT institution and General Manager of the G450C.

The Nikon immersion scanner will join existing 450mm infrastructure at the Albany NanoTech Complex in April of 2015 in accordance with the project timeline.  This critical milestone will enable G450C founding members and CNSE to perform 10nm and below, full wafer photolithography, while optimizing tool configuration and performance.

In July of 2013, New York’s Governor Cuomo announced a $350 million partnership between the newly merged CNSE/SUNYIT and Nikon to develop next generation 450mm photolithography technology. Nikon and the newly merged CNSE/SUNYIT brought about a first of its kind immersion lithography scanner online in less than 12 months, enabling the vital wafer exposures that will further advance the industry’s transition from the current 300mm wafer platform to the next generation 450mm wafer platform.  The wafers that presented at SEMICON West are the first produced in support of the G450C, a public-private partnership headquartered at the NanoTech complex in Albany, NY.

“Nikon is very pleased to have achieved this key milestone, and we are intent on beginning the next phase of this program, said Nikon Corporation Senior Vice President and Semiconductor Lithography Business Unit General Manager, Toshikazu Umatate. “450mm scanner development is progressing on target to deliver the performance and productivity innovations that will deliver reduced cost per die, which is essential for the continuation of Moore’s Law.”

To date, more than $350 million in 450mm wafer tools have been installed at the Albany NanoTech Complex.  With the arrival of the Nikon immersion photolithography tool, the investment will swell to over $700 million.

One the first fully patterned 450mm wafers produced using conventional 193 immersion lithography.