SEMI and Solid State Technology Announce the 2014 “Best of West” Award Finalists

Each year at SEMICON West, the largest and most influential microelectronics exposition in North America, the “Best of West” awards are presented by Solid State Technology and SEMI. The award was established to recognize contributors moving the industry forward with their technological developments in the microelectronics supply chain.

The 2014 Best of West Finalists are:

  • Microtronic: EAGLEview IV — EAGLEview IV is an automated macro defect wafer inspection system that provides industry leading throughput (3,000+ Wafers Per Day), defect detection accuracy, and wafer classification. EAGLEview IV resolves many of the problems of manual/micro wafer inspection by automating and standardizing wafer inspection. South Hall, Booth 729 (Category: Metrology and Test)
  • Nikon Corporation: NSR-S630D Immersion Scanner — The NSR-S630D ArF immersion scanner leverages the well-known Streamlign platform, incorporating further developments in stage, optics, and autofocus technology to deliver unprecedented mix-and-match overlay and focus control with sustained stability to enable the 10/7 nm node.  South Hall, Booth 1705 (Category: Wafer Processing Equipment)   
  • SPTS Technologies:  Rapier XE — Rapier XE is a new, 300mm, plasma etch module which can lower costs and increase yields for device manufacturers utilizing TSVs for 3D packaging.  Designed for via reveal applications, the new module offers blanket silicon etch rates typically 3-4x faster than competing systems. South Hall, Booth 1317 (Category: Wafer Processing Equipment)   

The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 9, 2014.

Sunny prospects await photovoltaics in 2014

By Jeff Dorsch

The long night in solar energy may be coming to an end.

The comeback from the doldrums of 2011-13 could be told in the stock price of SolarCity, an installer of solar panels for business, government, and homes. Since falling to about $10 a share in early 2013, SCTY shares hit a peak of more than $88 in March. After tailing off this spring, SolarCity’s stock has rebounded in recent weeks, closing on July 1 at $71.22 a share.

Semiconductor Equipment and Materials International last month reported that global bookings for photovoltaic manufacturing equipment were $296 million for the first quarter of 2014, a 44 percent gain from a year earlier. Q1 worldwide billings were $240 million, down 6 percent from the first quarter of 2013, SEMI said, resulting in a quarterly book-to-bill ratio of 1.24 – the first time that ratio has been above parity in three years.

PV equipment makers had to struggle through 2013 before seeing business pick up this year. The book-to-bill ratio for the fourth quarter of last year was 0.61. For all of 2013, billings totaled $1.22 billion, off by 49 percent from 2012’s $2.40 billion, while bookings were $736 million, down 17 percent from the previous year’s $883 million, according to SEMI. Customers in Asia represented 78% of 2013 billings.

The Intersolar North America conference and exhibition will run this week in conjunction with SEMICON West. The conference is scheduled for July 7-9 at the InterContinental Hotel, while the exhibition is July 8-10 at Moscone West.

The U.S. solar market saw 4.2 gigawatts installed last year, and the forecast for 2014 is that American solar power capacity will grow by 5.2 gigawatts to 6.3 gigawatts, according to NPD SolarBuzz.

Belgium’s imec continues to work on thin-film solar cells and silicon-based solar cells. Most of the latter are p-type silicon, but there is a shift toward n-type silicon in solar cells now, according to Philip Pieters, imec’s business development director. These n-type silicon solar cells are capable of an energy-conversion efficiency rate of 21.5 percent, a figure certified by Germany’s Fraunhofer ISE-CalLab. Meco Equipment Engineers worked with imec on the nickel/copper plating for the front contacts on the solar cells, which were fabricated on square substrates measuring 156 millimeters by 156mm.

These processes could be “easily updated” for industry’s use in volume production of silicon-based solar cells, Pieters said.

The Intersolar North America conference will have multiple sessions on photovoltaics, energy storage, and solar heating and cooling on all three days, along with workshops and special events.

Sunny prospects await photovoltaics in 2014, it is clear.

What’s next for semiconductor packaging?

By Jeff Dorsch

With mobile devices continuing to shrink in size and wearable electronics emerging as a new market for semiconductors, advanced packaging technologies are taking on increasing importance in the global supply chain. Aside from the 3DIC package/system-in-package area, what is going on in semiconductor packaging these days?

Flip-chip and wafer-level packaging, among other types of chip-scale packaging (CSP), are progressing in technology development and industry adoption. They are not new technologies, but the multiple types of CSPs continue to proliferate.

Wafer-level chip-scale packaging (WLCSP) is being employed in the iPhone and other mobile devices. TechSearch International forecasts that the number of devices in wafer-level packages will more than double over seven years, reaching nearly 36.8 billion devices in 2017.

STATS ChipPAC, one the world’s largest contractors in IC assembly and testing services, recently introduced an encapsulated wafer-level chip-scale package, which it says can help prevent damage to the chip during the surface-mounting process.

“WLCSP is a bare-die package that is constantly exposed to potential cracking, chipping and handling damages before or during the SMT process. This is particularly true for advanced node products where the die is very thin and dielectric layers are extremely fragile,” Dr. Han Byung Joon, executive vice president and chief technology officer of STATS ChipPAC, said in a statement. “As mobile device manufacturers tighten their technical specifications to reach new levels of reliability in their products, the industry will see more stringent component level and board-level reliability (BLR) requirements. eWLCSPTM is a robust packaging solution that cost-effectively addresses the increased durability requirements for our customers in advanced silicon nodes down to 28nm.”

Amkor Technology, another large provider of chip assembly and test services, has seen the percentage of its revenue from advanced products (including flip chip, wafer-level processing and related test services) increase from 40.5 percent in 2011 to 49.1 percent in 2013. The company offers three options in WLCSPCSPnl bump on repassivation, CSPnl bump on redistribution, and CSPn3. These packages can have from four to 196 solder balls.

Advanced Semiconductor Engineering, another of the Big 4 in IC assembly and test services, offers a number of advanced packaging types, such as WLCSP, flip-chip CSP, flip-chip package-in-package, flip-chip ball grid array and its Advanced Single Sided Substrate, trademarked as aS 3. These types can accommodate from six to 2,916 leads.

In 2013, ASE saw its percentage of packaging revenue from advanced packaging increase to 26.7 percent from 2012’s 23.6 percent.

There are many other types of advanced packages, including ball grid arrays (BGAs), bump chip carriers (BCCs), and thin quad flat packages (TQFPs). BGAs have a host of variations, such as flip-chip BGAs and thin BGAs. (Packaging is a big bowl of alphabet soup with all its acronyms – that’s another article.) Intel has been using BGA packages since the days of the Pentium II microprocessors and the first Celeron mobile processors. It currently employs a “Micro-FCBGA” package for its mobile processors, containing 479 solder balls.

Land grid arrays, which Intel is making greater use of in the last five years, are basically a BGA without the solder balls.

Bump chip carriers are used in cell phones, digital cameras, wireless local-area networks, and other products.

Amkor touts its thin quad flat packs for application-specific integrated circuits, controllers, digital signal processors, field-programmable gate arrays, PC chipsets, processors, programmable logic devices, and static random-access memories. There are a wide variety of quad flat package types.

Dynamic random-access memories get their own advanced packaging, too. Fine-pitch BGAs are used for high-speed DRAMs.

Technical sessions on advanced packaging will be featured on the first two days of SEMICON West. Tuesday, July 8, will see “Mobility and More – The M&Ms of Cost Beneficial Advanced Packaging” in the morning and “Embracing What’s NEXT – Devices & Systems for Big Data, Cloud and IoT” in the afternoon. (You may have heard of the Internet of Things, or IoT, by now.) The afternoon of Wednesday, July 9, will have “Driving Automotive Innovation – The Enabling Role of Semiconductor and IC Packaging.”

As always, it should be another interesting year in advanced packaging!

James C. Morgan Announces $1,000,000 “Challenge Grant” for High Tech Industry Workforce Development

James C. Morgan, chairman emeritus, Applied Materials, Inc., today announced his commitment to match up to $500,000 in donations to the SEMI Foundation. The SEMI Foundation supports STEM education and promotes career awareness in the areas of semiconductor and high-tech manufacturing and technology. Morgan announced the “challenge grant” — to secure $1 million of funding support for workforce development — during the SEMI Press Conference at SEMICON West 2014, the largest microelectronics manufacturing event in North America.

Morgan committed to pledging up to $500,000 to the SEMI Foundation and invited others in the high-tech industry to join him in contributing in blocks of $50,000 or more. Over the next three months, Morgan will match every contribution of $50,000 or more.  A “success” party is planned in October at Ferrari Silicon Valley, hosted by Art Zafiropoulo, CEO of Ultratech.

“Today, we all have a role in supporting students’ success in their academic and career goals,” said James Morgan. “The SEMI Foundation has gotten thousands of young people excited about the importance of math, science and the opportunities in high-tech careers through its dynamic High Tech U program. It is time for the industry to take the High Tech U program to the next level and achieve even greater impact. I encourage you to commit qualifying contributions during the challenge period to the SEMI Foundation.”

Through High Tech U, the SEMI Foundation has conducted more than 170 programs for both students and teachers with a combined impact on more than 350,000 individuals.  High Tech U programs consist of a three-day “hands-on” science-based curricula and interactive professional skills development program. SEMI held 20 programs in 2013 in Europe, Japan, Korea and the United States.  The Foundation plans to expand the impact of the High Tech U franchise through enhanced program development, portal-based student engagement and tracking, industry employment information assistance and other improvements.

“Jim and Becky Morgan epitomize leadership and generosity through their tireless work to foster education,” said Denny McGuirk, president and CEO of SEMI.  “We commend his numerous contributions to SEMI, our industry, and the youth who will occupy high-tech careers in the future. We also encourage others to accept the challenge and to support the SEMI Foundation.”

Morgan has an extensive history in business and philanthropy. He is chairman emeritus of Applied Materials. He previously served as chairman of the board from 1987 to 2009, and as chief executive officer from 1977 to 2003. Morgan is the recipient of the 1996 National Medal of Technology, IEEE Robert N. Noyce Medal, and Silicon Valley Leadership Group’s “Spirit of Silicon Valley Lifetime Achievement Award.” Morgan was vice chairman of the President’s Export Council in 2003. He was appointed to the 2002 U.S.-Japan private Sector Government Commission. From 1996 to 1997, Morgan served on the Commission on U.S. Pacific Trade and Investment Policy. From 1988 to 1992, he served on the National Advisory Committee on Semiconductors.

FinScale’s Quantum FinFET Aims to Revive Moore’s Law

FinScale Incorporated, the semiconductor device and process innovation company, today announced immediate availability of its qFinFETTM technology, a next generation 3D MOSFET architecture and manufacturable process readily transferable to foundries and integrated device manufacturers. Crafted from the combination of many unique device and process innovations by FinScale’s scientists, the qFinFET technology offers significant improvements in performance, power efficiency and circuit density, along with substantially lower leakage, parametric variability and manufacturing costs than available advanced node FinFET and planar technology alternatives. From a device design optimized for quantum effects, ballistic transport and the nano-material properties of silicon, this quantum FinFET device architecture will scale to the end of the silicon MOSFET era.

“The technology shift from planar to 3D device architectures has opened new degrees of freedom and exciting opportunities for new innovations,” said George Cheroff, a prominent IBM Research manager and semiconductor pioneer who envisioned and developed the first n-channel planar MOSFET process used for memory and logic circuits in computers. “The qFinFET technology elegantly combines the advantages of current FinFET and planar FD-SOI technologies, and mitigates their inherent weaknesses to provide a unifying platform that will put the semiconductor industry back on track with Moore’s Law.”

“FinScale’s qFinFET offers manufacturers a high-yield 3D process for building scalable aspect-ratio fins that can be formed without double patterning down to the 14/16 nm node, and provide increased performance and transistor width (W) per unit area,” said Jeffrey Wolf, president and chief executive officer at FinScale. “Resulting fin transistor topologies deliver additional area reductions, and offer designers further area-saving and performance-boosting opportunities to differentiate at the cell library and circuit level when integrated with leading middle-of-line (MOL) technologies.”

“We conceived the Quantum FinFET by pushing silicon to its quantum scaling limits, while seeking to maximize carrier mobility, electrostatic gate control, yield and reliability,” said Dr. Victor Koldyaev, Finscale’s chief technology officer. “Using this approach we designed the qFinFET front-end-of-line (FEOL) device and process solution for the 7 and 10nm generations, and were pleased that the same device concept would significantly boost parametric performance and economic returns for manufacturers back to the 28/32nm node. We then laid out standard cells, SRAMs, eDRAMs and 2-bit/cell non-volatile memories using industry standard design rules and realized that we could readily exceed the best published results at those nodes and give manufacturers and designers opportunities for further improvement.”

The qFinFET technology offers unique benefits for foundries and integrated device manufacturers. The included high density and high performance logic and memory configurations, along with inherent low-noise analog/RF device characteristics, make qFinFET a robust SoC platform, either on bulk or SOI substrates. Standalone DRAM, flash and SRAM memory designers and manufacturers can configure the included bit cells into dense arrays, and build dense, highly reliable sense amplifiers and low-leakage pass transistors.

FinScale will be presenting its qFinFET technology at the Silicon Innovation Forum (www.semiconwest.com/SIF) at the SemiconWest conference on July 8, 2014 in San Francisco at the Moscone Center. CEO Jeffrey Wolf will present FinScale’s investor pitch at 10:15am in the North Hall, room 134. Then from 4:00pm to 6:00pm Mr. Wolf and Dr. Victor Koldyaev will be presenting posters at the Silicon Innovation Forum Showcase and Reception.