Semiconductors

SEMICONDUCTORS ARTICLES



SUSS EUV lithography mask management system debuts with imec install

07/13/2011 

SUSS MicroTec unveiled MaskTrack Pro InSync, a holistic in-fab EUVL mask management product that synchronizes mask cleaning, handling, inspection, and storage.

MHI 8" wafer bonder produces 3D LSI ICs at room temp with FAB gun

07/13/2011  Mitsubishi Heavy Industries Ltd. (MHI) developed a fully automated 8" wafer bonding machine that bonds large-scale integration (LSI) circuits at room temperature, creating 3D ICs.

Cymer talks EUV, TCZ, light source monitoring upgrade

07/13/2011 

Nigel Farrar, Cymer, provides a status report on EUV lithography source technology, extensions to ArF lithography, the laser crystallization process from the company's TCZ display equipment product division, and Cymer's newest DUV source product the OnPulse Plus data monitoring system.

EUV lithography infrastructure update from SEMATECH

07/13/2011 

Stefan Wurm, SEMATECH, discusses EUV lithography's infrastructure. Want milestones? The first EUV litho beta tools have been delivered, and now the motivation is increasing throughput and reducing defects.

Top semiconductor metrology challenges from SEMATECH POV

07/13/2011 

At SEMICON West 2011, Phil Bryson, SEMATECH, covers the top challenges in semiconductor metrology at advanced nodes.

ASML tweaks immersion tool to improve imaging, overlay

07/13/2011 

ASML has added three extensions to its Twinscan NXT 1950i tool, to improve imaging, overlay, and system throughput.

GLOBALFOUNDRIES uses Intermolecular combinatorial method to improve wafer fab

07/13/2011 

GLOBALFOUNDRIES will use Intermolecular's High Productivity Combinatorial technology on research and development of its next-generation and mature semiconductor manufacturing lines.

Day 2: Intersolar wanderings, SEMICON West symposium

07/13/2011 

Techcet's Michael A. Fury reports from busy aisles at Intersolar, and at SEMICON West where a private symposium by CEA Leti reviewed work in FDSOI, 3D integration, TSVs, silicon photonics, and MEMS for medicine.

Novellus uncrates conformal films for sub-2Xnm

07/13/2011 

The Conformal Film Deposition (CFD) suite of dielectric films consists of oxide, doped oxide and nitride films that are deposited below 450

Thermal wafer processing for Ni(Pt)Si contacts beyond 45nm

07/12/2011 

The formation of advanced thin nickel-silicide films poses major challenges as devices integration moves beyond the 45nm technology node. X. Pages et al, Renesas Electronics, explain how optimized low-temperature rapid thermal processing (RTP) annealing schemes address this issue.

FDSOI improves CMOS scalability, speed, power consumption at 11nm

07/12/2011 

Leti has demonstrated the ability of fully depleted silicon on insulator (FDSOI) technology to improve CMOS scalability down to the 11nm node, together with an associated variability reduction of the electrical characteristics by a factor of two compared to regular technologies.

Olympus inspects bonded wafers with IR microscopy

07/12/2011 

Greg Baker, Olympus Integrated Technologies America, discusses why the company chose to focus its efforts on IR metrology for defect inspection of bonded wafers. Olympus-ITA launched the latest 3DIR Metrology and Defect Review System at SEMICON West 2011, booth 1524.

Suss joins imec's EUV mask integrity work

07/12/2011 

Suss Microtec and imec are expanding a research collaboration in mask cleaning to develop an in-fab approach to EUV lithography mask integrity, aiming to develop a sophisticated approach to preserving mask integrity prior to exposure.

Imec brings new device architecture results to SEMICON West

07/11/2011 

At SEMICON West, imec is demonstrating a viable implant-free quantum-well (IF-QW) pFETs with an embedded silicon-germanium (SiGe) source/drain and 3D integration of a commercial DRAM chip on top of a logic IC.

AMEC reactive ion etch tool enables sub-28nm nodes

07/11/2011 

AMEC launched its Primo 300mm very-high-frequency advanced decoupled reactive ion etch tool for sub-28nm. AMEC's Ben Lee describes the tool's mini-batch cluster architecture, and the physics that makes it work.

Extending optical lithography with complementary e-beam lithography

07/11/2011 

David Lam summarizes how the industry does not have to "throw out" optical lithography as it proceeds to more advanced nodes -- complementary e-beam lithography (CEBL) is part of the overall solution, "complementary lithography," that can overcome the resolution limitations of 193i technology.

EVG tool bonds 450mm SOI semiconductor wafers

07/11/2011 

EV Group (EVG) released a wafer bonding system for 450mm silicon-on-insulator (SOI) wafers: EVG850SOI/450-mm. EVG's Paul Lindner discusses the tool, and challenges of 450mm and SOI.

TSV moves to "real engineering," but reliability data needed

07/11/2011 

Jan Vardaman, president and founder of TechSearch International, summarizes highlights from her SEMICON West presentation on TSVs, speaking to RDL development, LED packaging, and TSV-alternative PoP.

450mm transition: 4 changes you must know

07/10/2011 

Bill Shaner, VP and GM, Microenvironments Division, Entegris, discusses key changes in the semiconductor manufacturing industry's move from 300 to 450mm wafers: Wafer fragility, wafer sag, increased weight, and higher capital investment.

Canon enters back-end packaging market with lithography tool debut

07/08/2011 

Canon Inc. made its first foray into the semiconductor back-end packaging equipment market with the new FPA-5510iV for through silicon via (TSV) and bump lithography.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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