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Applied Materials, Inc. today announced plans for the Materials Engineering Technology Accelerator (META Center), a major expansion of the company’s R&D capabilities aimed at creating new ways for Applied and its customers to drive innovation as classic Moore’s Law scaling becomes more challenging.

The primary goal of the META Center is to speed customer availability of new chipmaking materials and process technologies that enable breakthroughs in semiconductor performance, power and cost. The new center will complement and extend the capabilities of Applied’s Maydan Technology Center in Silicon Valley.

The META Center will be a hub for innovation, delivering on a call to action by Applied CEO Gary Dickerson for increased collaboration and speed across the technology ecosystem.

“Realizing the full potential of Artificial Intelligence and Big Data will require significant improvements in performance, power consumption and cost both at the edge and in the cloud,” said Gary Dickerson, president and CEO of Applied Materials. “The industry needs new computing architectures and chips enabled by innovative materials and scaling approaches. The META Center creates a new platform for working with customers to accelerate innovation from materials to systems.”

Scheduled to open in 2019, the META Center will be a first-of-its kind facility, spanning 24,000 square feet of cleanroom. It will be furnished with a broad suite of Applied’s most advanced process systems along with complementary technologies needed for new chip materials and structures to be piloted for high-volume production at customer sites.

To be located at the State University of New York Polytechnic Institute (SUNY Poly) campus in Albany, New York, the META Center will be created under agreements to be entered into with New York State, The Research Foundation for The State University of New York and SUNY Poly, that have been approved by the Empire State Development Board of Directors and are subject to further approval by The New York State Public Authorities Control Board.

“SUNY Poly provides an ideal combination of infrastructure, capabilities and talent in a thriving academic and entrepreneurial setting with deep roots in the semiconductor industry,” said Steve Ghanayem, senior vice president of New Markets and Alliances at Applied Materials. “The technology ecosystem will benefit from the acceleration of materials innovation through collaboration at the META Center.”

According to Samsung R&D, “We value our collaboration with Applied Materials on process development. The industry needs new innovations beyond traditional device scaling including the exploration of new materials. We are very pleased to see Applied Materials’ effort to expand its advanced R&D capabilities to provide added resources to customers and accelerate chip development.”

“TSMC welcomes closer collaboration with critical suppliers like Applied Materials in both equipment and materials,” said J.K. Lin, TSMC’s Vice President of Information Technology and Risk Management & Materials Management. “Working together to accelerate the industry’s innovation and address high-growth opportunities is very much in the spirit of TSMC’s Grand Alliance, the largest ecosystem in the semiconductor industry.”

“IBM and Applied Materials have a long history of collaboration in materials engineering to advance semiconductor industry breakthroughs,” said Dr. Mukesh V. Khare, IBM Research Vice President. “AI is one of the biggest opportunities of our time and will require innovations across materials, devices and architectures. We are pleased to see Applied expanding its capabilities to support the industry through the AI journey with its new META Center in Albany, New York.”

“As complexity increases and costs rise, traditional device scaling is slowing for the latest technology nodes,” said Tom Caulfield, CEO GLOBALFOUNDRIES. “It’s great to see Applied Materials investing in a broad range of advanced R&D capabilities to bring new and new combinations of materials into chip manufacturing, and I look forward to our continued collaborative efforts as we develop more differentiated solutions for our clients.”

“Delivering the improvements in performance and efficiency that allow Arm partners to continue to advance compute will mean overcoming the challenges presented by scaling transistors and interconnect in the deep nanometer process nodes,” said Greg Yeric, fellow, Arm. “There are many novel ideas being explored in this area, but the timeline from concept to production needs to be accelerated, and the expansion of Applied Materials’ R&D capabilities will help enable this research to advance at a faster pace.”

“Applied Materials is the world leader in semiconductor process and tools,” said Kurt Busch, CEO of Syntiant Corp. “We strongly value our relationship with Applied Materials and look forward to the benefits their latest technology will bring to breakthrough edge device machine learning products.”

Micron Technology, Inc., (Nasdaq: MU) today announced that it has begun mass production of the industry’s highest-capacity and first monolithic 12Gb low-power double data rate 4x (LPDDR4x) DRAM for mobile devices and applications. This latest generation of Micron’s LPDDR4 memory brings key improvements in power consumption while maintaining the industry’s fastest LPDDR4 clock speeds, thereby delivering advanced performance for next-generation mobile handsets and tablets. In addition, Micron’s 12Gb LPDDR4x doubles memory capacity to offer the industry’s highest-capacity monolithic LPDDR4 without increasing the footprint compared to the previous generation product.

The exponential increase in usage of compute and data-intensive mobile applications such as artificial intelligence (AI), augmented reality (AR) and 4K video has been accompanied with demands by mobile users to maximize battery life and performance and increase capacity. Next-generation mobile devices that integrate multiple high-resolution cameras and increasingly use AI for image optimization also require higher DRAM capacities to support these features.

As the industry transitions towards deployment of 5G mobile technology, the memory subsystem in mobile handsets will have to support these dramatically higher data rates and the associated processing of data in real-time. New applications built upon 5G technology will also be able to leverage the increased capabilities of the memory subsystem to enable new and immersive user experiences.

As the industry’s highest-capacity monolithic mobile memory, Micron’s LPDDR4x DRAM delivers industry-leading bandwidth and power efficiency, along with the benefit of enabling higher DRAM capacities in the handset.

“Micron is a recognized pioneer in bringing low-power DRAM technology to the world and we once again have delivered another milestone with the launch of the industry’s first, highest-capacity monolithic 12Gb mobile DRAM,” Senior Vice President and General Manager of Micron’s Mobile Business Unit Raj Talluri said. “This latest generation of LPDDR4 enables mobile handset manufacturers to deliver a rich user experience for ultra-slim mobile devices as user demands for performance, capacity and longer battery life continue to rise as a result of data-intensive applications.”

The LPDDR4x DRAM will be produced based on 1Y-nm (10-nanometer-class) process technology, resulting in improved efficiency and reduction in battery power consumption. Micron’s LPDDR4x mobile DRAM is capable of reducing power by up to 10 percent at similar data rates of 4,266 megabits per second (Mb/s) compared to previous generations.

Micron 12Gb LPDDR4 memory solutions are available today. For more information, visit www.micron.com.

IC Insights’ November Update to The 2018 McClean Report will present an in-depth analysis and detailed five-year forecast for the IC Industry, which is expected to enter a period of cyclical “cooling” after an extended period of very strong growth.

Figure 1 illustrates the worldwide quarterly year-over-year IC market increases from 1Q through 3Q and IC Insights’ forecast for 4Q of this year.  As shown, the first half of 2018 started out with strong quarterly year-over-year growth for the IC market.  However, year-over-year IC market growth dropped to 14% in 3Q.  Moreover, with the softening of the memory market, IC Insights projects that year-over-year IC market growth in 4Q will be only 6%.

Figure 1

Third quarter sequential growth confirms the slowing year-over-year trend. In 2017, 3Q/2Q IC market growth was 11%.  This year, 3Q/2Q growth slowed to a 6% increase (the same rate as the long term average).  As mentioned, the softening memory market has started to become a “headwind” on total IC market growth.  It is interesting that in 2017, the 3Q/2Q memory market growth rate was a very strong 18%.  In contrast, the 3Q/2Q memory market increase in 2018 was 8%, less than half of last year’s rate.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $122.7 billion during the third quarter of 2018, an increase of 4.1 percent over the previous quarter and 13.8 percent more than the third quarter of 2017. Global sales for the month of September 2018 reached $40.9 billion, an uptick of 2.0 percent over last month’s total and 13.8 percent more than sales from June 2017. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Three-quarters of the way through 2018, the global semiconductor industry is on pace to post its highest-ever annual sales, comfortably topping last year’s record total of $412 billion,” said John Neuffer, president and CEO, Semiconductor Industry Association. “While year-to-year growth has tapered in recent months, September marked the global industry’s highest-ever monthly sales, and Q3 was its top-grossing quarter on record. Year-to-year sales in September were up across every major product category and regional market, with sales into China and the Americas continuing to lead the way.”

Regionally, sales increased compared to September 2017 in China (26.3 percent), the Americas (15.1 percent), Europe (8.8 percent), Japan (7.2 percent), and Asia Pacific/All Other (2.4 percent). Sales were up compared to last month in the Americas (6.0 percent), China (1.8 percent), and Europe (1.2 percent), but down slightly in Asia Pacific/All Other (-0.1 percent) and Japan (-0.6 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

September 2018
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 8.68 9.20 6.0%
Europe 3.53 3.57 1.2%
Japan 3.39 3.37 -0.6%
China 14.10 14.35 1.8%
Asia Pacific/All Other 10.43 10.42 -0.1%
Total 40.12 40.91 2.0%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 7.99 9.20 15.1%
Europe 3.28 3.57 8.8%
Japan 3.14 3.37 7.2%
China 11.36 14.35 26.3%
Asia Pacific/All Other 10.18 10.42 2.4%
Total 35.95 40.91 13.8%
Three-Month-Moving Average Sales
Market Apr/May/Jun Jul/Aug/Sept % Change
Americas 8.34 9.20 10.2%
Europe 3.67 3.57 -2.7%
Japan 3.39 3.37 -0.8%
China 13.59 14.35 5.6%
Asia Pacific/All Other 10.32 10.42 1.0%
Total 39.31 40.91 4.1%

By Jay Chittooran

Last week, the Office of the U.S. Trade Representative (USTR), on instruction from President Trump, notified Congress that the administration intends to begin bilateral trade negotiations with Japan, the European Union (EU), and the United Kingdom.

SEMI stands strong for free trade and open markets, and roundly supports efforts to increase market access and tap into more foreign economies, especially economies like Japan and the EU, both of which are central to the semiconductor industry. The semiconductor industry, which enables the $2 trillion electronics market, is built on global commerce. SEMI members rely on a vast network of supply chains that span the globe, bringing together components and tools made all around the world and assembled into a single sub-system that is then integrated into a larger tool used in the chipmaking process.

These free trade agreements will reduce tariffs, which will result in cost savings and productivity gains, and allow SEMI members to expand and grow. But the benefits of modern free trade agreements extend well beyond tariff reduction. Indeed, these trade deals will establish and enhance global trade rules that enable companies to innovate and compete fairly on a level playing field. Trade agreements strengthen certainty and further business continuity.

While the exact nature and negotiation timelines for the talks remain unclear, SEMI will engage the administration, urging it to maintain high standards in these agreements, such as:

  • Maintain strong respect for intellectual property and trade secrets through robust safeguards and significant penalties for violators
  • Remove tariffs and non-tariff barriers on semiconductor products as well as products that depend on semiconductors
  • Simplify and harmonize the customs and trade facilitation processes
  • Combat any attempts of forced technology transfer
  • Prevent use of data localization measures and enable the free flow of cross-border data flows
  • End discriminatory and/or burdensome regulatory practices
  • Ensure standards in all forms are market-oriented
  • Create rules for state-owned enterprises to ensure fair and non-discriminatory treatment of all companies

According to Trade Promotion Authority (TPA), the U.S. law that guides trade votes in Congress, negotiations with each country can only begin 90 days after last week’s notification. During that period, there will be intensive consultation with Congress and stakeholders. This means, at the earliest, talks can start on January 14, 2019. (Bear in mind that discussions with the UK can only begin in earnest once the UK has formally left the European Union on March 29, 2019.)

The Trump administration’s announcement comes after the U.S. imposed or threatened tariffs on imports on all trading partners, including the EU and China. All told, the U.S. has imposed tariffs on more than $300 billion worth of goods. SEMI has weighed in on the detrimental nature of tariffs, arguing that tariffs on China will ultimately do nothing to address the concerns with China’s trade practices. This sledgehammer approach will introduce significant uncertainty, impose greater costs, and potentially lead to a trade war, ultimately undercutting the ability of semiconductor companies to sell overseas, stifling innovation and curbing U.S. technological leadership.

Elsewhere, the Comprehensive and Progressive Agreement for Trans-Pacific Partnership, the multilateral trade deal that links 11 Asia-Pacific economies, is well on its way to taking force. Canada will be taking its final steps to ratify the deal, joining Mexico, Japan and Singapore. The deal, formerly known as the Trans-Pacific Partnership, should take effect by the first half of 2019.

SEMI will continue tracking ongoing trade developments. Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Total wafer shipments in 2018 year are expected to eclipse the all-time market high set in 2017 and continue to reach record levels through 2021, according to SEMI’s recent semiconductor industry annual silicon shipment forecast. The forecast of demand for silicon units for the period 2018 through 2021 shows polished and epitaxial silicon shipments totaling 12,445 million square inches in 2018; 13,090 million square inches in 2019; 13,440 million square inches in 2020, and 13,778 million square inches in 2021 (see table below).

“As new greenfield fab projects continue to emerge for memory and foundry, silicon shipments are expected to remain strong for 2019 and through 2021,” said Clark Tseng, director of Industry Research & Statistics at SEMI. “Silicon demand will continue to grow as semiconductor content increases in mobile, high-performance computing, automotive, and Internet of Things applications.”

2018 Silicon* Shipment Forecast (MSI = Millions of Square Inches)

Annual Growth

*Total Electronic Grade Silicon Slices – Excludes Non-Polished Wafers

*Shipments are for semiconductor applications only and do not include solar applications

Source: SEMI (www.semi.org), October 2018

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or chips are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

By Serena Brischetto

SEMI met with Heinz Martin Esser, managing director at Fabmatics GmbH, to discuss how existing 200mm semiconductor fabs can master the challenges of a 24×7 production under highest cost and quality pressure by implementing intralogistics automation solutions. The two spoke ahead to his presentation at the Fab Management Forum at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here.

SEMI: Looking at the latest production capacity data for 2018 – it is a 200mm fab boom. Growing demand for analog, MEMS and RF chips continues to cause acute shortages for both 200mm fab capacity and equipment. Do you think this trend will continue the next years or is it only a short term run on 200mm fabs?

Esser: We at Fabmatics believe in a long-term trend. The emergence of the Internet of Things and growing digitalization in all areas of life will continue to increase demand for integrated circuits (ASICs), analog ICs, high-performance components and micro-mechanical sensors (MEMS) in the coming years. Many of these semiconductor elements should be produced in 200 mm fabs.

SEMI: How does Fab automation contribute to increase capacity of existing, mature 200mm fabs?

Esser:  We are convinced that fab automation is one of the greatest potentials for older 200mm factories to effectively master increased demand, increasing efficiency, quality assurance and flexibility at the same time. In particular, material flow automation, which is often the missing link between existing equipment in different production areas, can help increase productivity in an elementary way.

If you analyze how long valuable tools typically wait for loading and unloading, you can see a direct effect of the intralogistics automation system, which leads to a significantly higher utilization of process equipment by making the material flow independent from human performance. Additional side effects such as reduced cycle time, stable fab flow factor or flattened WIP shafts further increase the contribution of material flow automation to get the most out of existing mature factories. Older does not mean obsolete.

SEMI: What are the biggest challenges for a successful implementation?

Esser: There is no single challenge when you automate an existing mature fab. Instead, you face a whole variety of challenges you have to tackle, ranging from historically grown non-aligned fab layouts over non-linear material flows and older non-standardized equipment to “automation unfriendly” fab environment. Also you should not underestimate the efforts to overcome the practice manual fab operation people in the cleanroom are so familiar with for many years. Before doing automation you have to think automation, i.e. you have to question all processes to make them ready for automation.

SEMI: What are the key drivers to automate a mature fab today: costs, process stability, quality or a combination of them?

Esser: This question should be better asked to our customers, but we believe it is a mix of many impacts. Most likely everybody sees the cost reduction at first, but we get more aware of process and performance stability as well as quality requirements – and here our customers’ play the most important role – become more and more focused.

SEMI: What do you expect from SEMICON Europa 2018 and why do you recommend attending the Fab Management Forum?

Esser: This year SEMICON Europa will co-locate with electronica. So it`s going to be the greatest trade fair for electronics manufacturing in Europe. We will meet innovators and decision-makers across the whole electronics supply chain.

The Fab Management Forum addresses a highly topical question that concerns all semiconductor manufacturers not only in Europe – how to handle complexity and enable the necessary flexibility to cope with customers’ needs. High-ranking speakers will give an insight into the latest technologies and best practices. I am looking forward to the lively exchange with the participants and taking away new impulses for our business.

Heinz Martin Esser is managing director at Fabmatics GmbH, responsible for sales and marketing, customer service and administration. He studied supply engineering at the University of Applied Sciences in Cologne and later earned a university degree in business administration.

Originally published on the SEMI blog.

To scale down a transistor below a 5nm node is one of the vital concerns for VLSI industry as there are various challenges due to the shrinking of components. Several researches are going on worldwide to overcome the challenges of future technology nodes. Among them, this article reviews the potential transistor structures and materials like Carbon Nano-tube FET, Gate-All-Around FET, and Compound Semiconductors as solutions to overcome the problems of scaling the existing silicon FinFET transistor below 5nm node.

By Pavan H Vora, Akash Verma, Dhaval Parikh

The ‘Semiconductor era’ started in 1960 with the invention of the integrated circuit. In an integrated circuit, all the active-passive components and their interconnection are integrated on a single silicon wafer, offering numerous advantages in terms of portability, functionality, power, and performance. The VLSI industry is following Moore’s law for many decades, which says, “the number of transistors on a chip becomes double approximately every two years”. To get the benefits of a scaled-down transistor, VLSI industry is continuously improving transistor structure and material, manufacturing techniques, and tools for designing IC. Various techniques, which have been adopted for transistors so far, include high-K dielectric, metal gate, strained silicon, double patterning, controlling channel from more than one side, silicon on insulator and many more techniques. Some of these techniques are discussed in ‘A Review Paper on CMOS, SOI and FinFET Technology’[1].

Nowadays, the demand of the internet of things, autonomous vehicles, machine learning, artificial intelligence, and internet traffic is growing exponentially, which acts as a driving force for scaling down transistor below the existing 7nm node for higher performance. However, there are several challenges of scaling down a transistor size.

Issues with Sub-Micron Technology:

Every time we scale down a transistor size, a new technology node is generated. We have seen transistor sizes such as 28nm, 16nm, etc. Scaling down a transistor enables faster switching, higher density, low power consumption, lower cost per transistor, and numerous other gains. The CMOS (complementary metal-oxide-semiconductor) transistor base IC technology performs well up to 28nm node. However, the short channel effects become uncontrollable if we shrink down CMOS transistor below 28 nm. Below this node, a horizontal electric field generated by drain-source supply tries to govern the channel. As a result, the gate is unable to control leakage paths, which are far from the gate.

16nm/7nm Transistor Technology: FinFet and FD-SOI:

The VLSI industry has adopted FinFET and SOI transistor for 16nm and 7nm nodes, as both the structures are able to prevent the leakage issue at these nodes. The main objective of both the structures is to maximize gate-to-channel capacitance and minimize drain-to-channel capacitance[1]. In both transistor structures, the channel thickness scaling is introduced as the new scaling parameter. As the channel thickness is reduced, there are no paths, which are far from the gate area. Thus, gates have a good control over the channel, which eliminates short channel effects.

In Silicon-on-Insulator (SOI) transistor, a buried oxide layer is used, which isolates the body from the substrate shown in Figure 1(a).Owing to the BOX layer, drain-source parasitic junction capacitances are reduced, which results in faster switching. The main challenge with the SOI transistor is that it is difficult to manufacture a thin silicon layer on the wafer.

Figure 1: a) FD-SOI Structure b) FinFET Structure and Channel

FinFET, which is also called as tri-gate controls channel is shown from three sides in Figure 1(b).  There is a thin vertical Si-body, which looks like a back fin of fish wrapped by the gate structure. A width of the channel is almost two times Fin height. Thus, to get higher driving strength, a multi-Fin structure is used. One of the gains with FinFET is higher driving current. The main challenge with FinFET is the complex manufacturing process.

Challenges with Technology Node below 5nm: What Next?

Reducing the body thickness results into lower mobility as surface roughness scattering increases. Since FinFET is a 3-D structure, it is less efficient in terms of thermal dissipation. Also, if we scale down the FinFET transistor size further, say below 7nm, the leakage issue becomes dominant again. Consequently, many other problems come into consideration like self-heating, threshold flattening, etc. These concerns lead to research on other possible transistor structures and replacing existing materials with new effective materials.

According to the ITRS roadmap (International Technology Roadmap for Semiconductors), the next technology nodes are 5nm, 3nm, 2.5nm, and 1.5nm. Many different types of research and studies are going on in VLSI industry and academia for potential solutions to deal with these future technology nodes. Here we discuss some promising solutions like carbon nanotube FET, GAA transistor structure, and compound semiconductor for future technology nodes.

Figure 2: Transistor Technology Roadmap

CNTFET – Carbon Nano Tube FET:

CNT (Carbon Nanotube) showcases a new class of semiconductor material that consists of a single sheet of carbon atoms rolled up to form a tubular structure. CNTFET is a field-effect transistor (FET) that uses semiconducting CNT as a channel material between the two metal electrodes, which behave as source and drain contacts. Here we will discuss carbon nanotube material and how it is beneficial to FET at a lower technology node.

  • What is a Carbon Nanotube?

CNT is a tubular shaped material, made of carbon, having diameters measurable on the nanometer scale. They have a long and hollow structure and are formed from sheets of carbon that are one atom thick. It is called “Graphene”. Carbon nanotubes have varied structures, differing in length, thickness, helicity, and the number of layers. Majorly, they are classified as Single Walled Carbon Nanotube (SWCNT) and Multi-Walled Carbon Nanotube (MWCNT). As shown in Figure 3(a), one can see that SWCNTs are made up of a single layer of graphene, whereas MWCNTs are made up of multiple layers of graphene.

Figure 3: a) Single Walled and Multi Walled CNTs b) Chirality Vector Representation

  • Properties of Carbon Nanotube:

The carbon nanotube delivers excellent properties in areas of thermal and physical stability as discussed below:

  1. Both Metallic and Semiconductor Behavior

The CNT can exhibit metallic and semiconductor behavior. This change in behavior depends on the direction in which the graphene sheet is rolled. It is termed as chirality vector. This vector is denoted by a pair of integer (n, m) as shown in Figure 3(b). The CNT behaves as metallic if ‘n’ equals to ‘m’ or the difference of ‘n’ and ‘m’ is the integral multiple of three or else it behaves as a semiconductor [2].

  1. Incredible Mobility

SWCNTs have a great potential for application in electronics because of their capacity to behave as either metal or as a semiconductor, symmetric conduction and their capacity to carry large currents. Electrons and holes have a high current density along the length of a CNT due to the low scattering rates along the CNT axis. CNTs can carry current around 10 A/nm2, while standard metal wires have a current carrying capacity that is only around 10 nA/nm2[3].

  1. Excellent Heat Dissipation

Thermal management is an important parameter for the electronic devices’ performance. Carbon nanotubes (CNTs) are well-known nanomaterials for excellent heat dissipation. Moreover, they have a lesser effect of the rise in temperature on the I-V characteristics as compared to silicon [4].

CNT in Transistor Applications: CNFET

The bandgap of carbon nanotubes can be changed by its chirality and diameter and thus, the carbon nanotube can be made to behave like a semiconductor. Semiconducting CNTs can be a favorable candidate for nanoscale transistor devices for channel material as it offers numerous advantages over traditional silicon-MOSFETs. Carbon nanotubes conduct heat similar to the diamond or sapphire. Also, they switch more reliably and use much less power than silicon-based devices [5].

In addition, the CNFETS have four times higher trans-conductance than its counterpart. CNT can be integrated with a High-K material, which is offering good gate control over the channel. The carrier velocity of CNFET is twice as compared to MOSFET, due to increased mobility. A carrier mobility of N-type and P-type CNFET is similar in offering advantages in terms of same transistor size. In CMOS, PMOS (P-type metal-oxide-semiconductor) transistor size is approximately 2.5 times more than NMOS (N-type metal-oxide-semiconductor) transistor as mobility values are different.

The Fabrication process of CNTFET is a very challenging task as it requires precision and accuracy in the methodologies.Here we discuss the Top-gated CNTFET fabrication methodology.

The first step in this technique starts from the placement of carbon nanotubes onto the silicon oxide substrate. Then the individual tubes are isolated. Source and drain contacts are defined and patterned using advanced lithography. The contact resistance is then reduced by refining the connection between the contacts and CNT. The deposition of a thin top-gate dielectric is performed on the nanotube via evaporation technique. Lastly, to complete the process, the gate contact is deposited on the gate dielectric [6].

Figure 4: Concept of Carbon-Nanotube FET

Challenges of CNTFET:

There are lots of challenges in the roadmap of commercial CNFET technology.  Majority of them have been resolved to a certain level, but a few of them are yet to be overcome. Here we will discuss some of the major challenges of CNTFET.

  1. Contact Resistance

For any advanced transistor technology, the increase in contact resistance due to the low size of transistors becomes a major performance problem. The performance of the transistor degrades as the resistance of contacts increases significantly due to the scaling down of transistors. Until now, decreasing the size of the contacts on a device caused a huge drop in execution — a challenge facing both silicon and carbon nanotube transistor technologies [7].

  1. Synthesis of Nanotube

Another challenge with CNT is to change its chirality such that it behaves like a semiconductor. The synthesized tubes have a mixture of both metals and semiconductors. But, since only the semiconducting ones are useful for qualifying to be a transistor, engineering methodologies need to be invented to get a significantly better result at separating metal tubes from semiconducting tubes.

  1. To develop a non-lithographic process to place billions of these nanotubes onto the specific location of the chip poses a challenging task.

Currently, many engineering teams are carrying out research about CNTFET devices and their logic applications, both in the industries and in the universities. In the year 2015, researchers from one of the leading semiconductor companies succeeded in combining metal contacts with nanotubes using “close-bonded contact scheme”. They achieved this by putting a metal contact at the ends of the tube and making them react with the carbon to form different compounds. This technique helped them to shrink contacts below 10 nanometers without compromising the performance [8].

Gate-All-Around FET: GAAFET

One of the futuristic potential transistor structures is Gate-all-around FET. The Gate-all-around FETs are extended versions of FinFET. In GAAFET, the gate material surrounds the channel region from the four directions. In a simple structure, a silicon nanowire as a channel is wrapped by the gate structure. A vertically stacked multiple horizontal nanowires structure is proven excellent for boosting current per given area. This concept of multiple vertically stacked gate-all-around silicon nanowire is shown in Figure 5.

Figure 5: Vertically Stacked Nanowires GAAFET

Apart from silicon material, some other materials like InGaAs, germanium nanowires can also be utilized for better mobility.

There are many hurdles for GAAFET in terms of complex gate manufacturing, nanowires, and contacts. One of the challenging processes is fabricating nanowires from the silicon layer as it requires a new approach for the etching process.

There are many research labs and institute working for Gate-all-around FET for lower nodes. Recently, Leuven based R&D firm claimed that they achieved excellent electrostatic control over a channel with GAAFET at sub 10nm diameter nanowire. Last year, one of the leading semiconductor companies unveiled a 5nm chip, which contains 30 billion transistors on a 50mm2chip using stacked nanowire GAAFET technology. It claimed to achieve 40% improvement in performance compared to 10nm node or 70% improvement in power consumption at the same performance.

Compound Semiconductors:

Another promising way to scale down a transistor node is the selection of novel material that exhibits higher carrier mobility. A compound semiconductor with ingredients from columns III and V are having higher mobility compared to silicon. Some compound semiconductor examples are Indium Gallium Arsenide (InGaAs), Gallium Arsenide (GaAs), and Indium Arsenide (InAs). According to various studies, integration of compound semiconductor with FinFET and GAAFET showing excellent performance at lower nodes.

The main concerns with compound semiconductor are large lattice mismatch between silicon and III-V semiconductor, resulting in defects of the transistor channel. One of the firms developed a FinFET containing V-shaped trenches into the silicon substrate. These trenches filled with indium gallium arsenide and forming the fin of the transistor. The bottom of the trench is filled with indium phosphide to reduce the leakage current. With this trench structure, it has been observed that defects terminate at the trench walls, enabling lower defects in the channel.


From the 22nm node to 7nm node, FinFETs have been proven successful and it may be scaled down to one more node. Beyond that, there are various challenges like self-heating, mobility degradation, threshold flattening, etc. We have discussed how carbon nanotube’s excellent properties of motilities, heat dissipation, high current carrying capability offer promising solutions for replacing existing silicon technology. As the stack of horizontal nanowire opened a “fourth gate”, Gate-all-around transistor structure is also a good candidate for replacing vertical Fin structure of FinFET for achieving good electrostatic property. It is not clear what comes next in the technology roadmap. However, in the futuristic transistor technology, there must be changes of existing material, structure, EUV (Extreme ultraviolet) lithography process, and packaging to sustain Moore’s law.


[1]  Pavan Vora, Ronak Lad, “A Review Paper on CMOS, SOI and FinFET Technology”, www.design-reuse.com/articles/

[2]  P.A Gowri Sankar, K. Udhaya Kumar, “Investigating The Effect of Chirality On Coaxial Carbon Nanotube Field Effect Transistor”, 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET)

[3] Rashmita Sahoo, S.K Sahoo, “Design of an efficient CNTFET using optimum number of CNT in channel region for logic gate implementation”, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

[4] Yijian Ouyang and Jing Guo, “Heat dissipation in carbon nanotube transistors”, Appl. Phys. Lett. 89, 183122 (2006)

[5] Philip G. Collins & Phaedon Avouris, “Nanotubes for Electronics”, Scientific American 283, 62 – 69 (2000)

[6] Wind, S. J.; Appenzeller, J.; Martel, R.; Derycke, V.; Avouris, Ph. (2002). “Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes”, Applied Physics Letters. 80 (20): 3817. Bibcode:2002ApPhL..80.3817W.

[7] Aaron D. Franklin, Wilfried Haensch, “Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors”, 72nd Device Research Conference

[8] IBM, “IBM Research Breakthrough Paves Way for Post-Silicon Future with Carbon Nanotube Electronics”, https://www-03.ibm.com/press/us/en/pressrelease/47767.wss

About Authors:

Pavan Vora

Pavan Vora is working as an ASIC Physical Design Engineer at eInfochips, an Arrow company. He has more than 3 years of experience in ASIC designs for cutting technology nodes such as 12nm, 16nm FinFET, and 28nm. Pavan has expertise in ASIC P&R, LEC, LVS, Static Timing Analysis, Signal EM, DRC, and IR drop and has been awarded a Gold Medal in Master of Engineering in VLSI System Design.

Akash Verma

Akash Verma is working as an ASIC Trainee Engineer at eInfochips, an Arrow company. He has completed his bachelors in Electronics & Communication from the GIT, Gandhinagar. He is currently working on networking ASIC chip at 7nm FinFET technology, in which his accountabilities include block level APR, Static Timing Analysis and Physical Verification. His interest lies in Analog Mixed Signal designs and EDA tool’s algorithmic methodologies.

Dhaval Parikh

Dhaval Parikh is working as a Technical Manager at eInfochips, an Arrow company. He has more than 11 years of industry experience and has worked in various ASIC designs of IP’s & SoC’s, from 180nm to cutting technology node 7nm. He has been responsible for all the aspects of physical design and verification along with executing multiple projects simultaneously.

About eInfochips:

eInfochips, an Arrow company, is a global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company’s service offerings include digital transformation and connected IoT solutions across various cloud platforms, including AWS and Azure.

Along with Arrow’s $27B in revenues, 19,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients through Arrow Connect.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, to day announced worldwide sales of semiconductors reached $40.16 billion for the month of August 2018, an increase of 14.9 percent compared to the August 2017 total of $34.96 billion. Global sales in August 2018 were 1.7 percent higher than the July 2018 total of $39.49 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales continued to bound upward in August, easily outperforming sales from last August and narrowly surpassing last month’s total,” said John Neuffer, president and CEO, Semiconductor Industry Association. “While year-to-year growth has moderated somewhat in recent months, sales remain strong across every major semiconductor product category and regional market, with the China and Americas markets standing out with the largest year-year growth.”

Regionally, sales increased compared to August 2017 in China (27.3 percent), the Americas (15.0 percent), Europe (9.5 percent), Japan (8.4 percent), and Asia Pacific/All Other (4.7 percent). Sales were up compared to last month in China (2.1 percent), the Americas (3.6 percent), and Asia Pacific/All Other (1.3 percent), and decreased slightly inJapan (-0.1 percent), and Europe (-1.4 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

By Jaegwan Shim

Korea is on track to top all other regions in fab investment, spending $63 billion between 2017 and 2020, with powerhouses Samsung Electronics Co. and SK Hynix leading the way, according to latest World Fab Forecast Report by SEMI. Samsung Electronics increased fab investments $770 million to $12 billion this year, and SK Hynix upped its spending a significant $2.8 billion to $7.25 billion in 2018.

Korea’s investment companies anticipate continued growth for both companies in the second half of 2018.

Under this halo of extraordinary investment, nearly 380 SEMI Korea members and industry analysts gathered for 2018 SEMI Korea Members Day on September 22 to share insights on semiconductor market trends and new technologies that could help members bolster their competitiveness. Following are key takeaways from the event.

Korea semiconductor market to grow 16% in 2018

That’s according to IDC Korea VP Kim Soo-kyung, who noted that data center, memory and Internet of Things (IoT) are becoming key growth drivers for the semiconductor industry. He encouraged semiconductor companies to closely track development of automotive technology and the industry semiconductor market, both key growth areas.

SEMI Korea president H.D. Cho opens SEMI Korea Members Day 2018

Continuing fab investment will lead to oversupply, but display will shine

Market entry by Chinese companies will also spur the oversupply, said Jeong Won-Seok, an analyst at HI Investment Corp. He noted that the oversupply will force Korea into stiffer competition with other regions. However, with OLED used for a wide variety of devices and the display industry seeing rapid growth, the sector will remain ripe for growth among Korean companies.

Interconnecting various applications is a big semiconductor industry trend

The need for these interconnections will stand out in the mobility and high-performance computing (HPC) markets, said Kim Jin-Young, director at Amkor Technology Korea, who addressed trends in packaging technology. He also emphasized interconnection cost efficiency as key to maximizing competitiveness.

Smart Manufacturing is driving mass customization

As semiconductor industry growth continues, production methods are shifting from ‘mass production’ to ‘mass customization,’ increasing the importance of Smart Manufacturing in driving greater production efficiency, noted BISTel VP Jeon Kyeong-Sik. Building a Smart Manufacturing platform to support large-scale production of specialized database and artificial intelligence (AI) chips will boost production efficiency, reduce costs and improve risk management. Virtual simulation will be a key enabling technology.

SEMI analyst Clark Tseng presenting at SEMI Korea Members Day 2018

Surge in data volume and technology advances to drive long-term semiconductor industry growth

These key industry drivers will continue to power fab investment growth, with spending focused on 3D NAND, DRAM, and foundry, said Clark Tseng, a SEMI analyst. China alone will see eye-watering growth with the region’s investments in domestic companies surging 46% from 2018 to 2019 and fab investment by Chinese domestic companies outpacing spending by foreign companies in China, Tseng predicted.

SEMI membership rises with industry growth

Culminating the event, SEMI Korea president H.D. Cho said, “With the growth of the semiconductor market, the number of SEMI members is gradually increasing, and we will help member companies grow with various activities such as Korea Members Day.”

Jaegwan Shim is a marketing specialist at SEMI Korea. 

Originally published on the SEMI blog.