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By David W. Price, Douglas G. Sutherland, Jay Rathert, John McCormack and Barry Saville

Author’s Note:The Process Watch series explores key concepts about process control—defect inspection, metrology and data analytics—for the semiconductor industry. This article is the third in a series on process control strategies for automotive semiconductor devices. For this article, we are pleased to include insights from our colleagues at KLA-Tencor, John McCormack and Barry Saville. 

Semiconductors continue to grow in importance in the automotive supply chain, requiring IC manufacturers to adapt their processes to produce chips that meet automotive quality standards. The first article in this seriesfocused on the fact that the same types of IC manufacturing defects that cause yield loss also cause poor chip reliability and can lead to premature failures in the field. To achieve the high reliability required in automotive ICs, additional effort must be taken to ensure that sources of defects are eliminated in the manufacturing process. The second article in this seriesoutlined strategies, such as frequent tool monitoring and a continuous improvement program, that reduce the number of defects added at each step in the IC manufacturing process. This article explores how to drive tool monitoring to a higher level of performance in order to help automotive IC manufacturers achieve chip failure rates below the parts per billion level.

As a reminder, tool monitoring is the established best practice for isolating the source of random defectivity contributed by the fab’s process tools. During tool monitoring, a bare wafer is inspected to establish its baseline defectivity, run through a specific process tool (or chamber), and then inspected again. Any defects that were added to the wafer must have come from that specific process tool. This method can reveal the cleanest “golden” tools in the fab, as well as the “dog” tools that contribute the most defects and require corrective action. With plots of historical defect data from the process tools, goals and milestones for continuous improvement can be implemented.

When semiconductor fabs design their tool monitoring strategy, they must decide on the minimum size of defects that they want to detect and monitor. If historical test results have shown that smaller defects do not impact yield, then fabs will run their inspection tools at a lower sensitivity so that they no longer detect these smaller defects. By doing this, they can focus only on the larger yield-killer defects, avoiding distraction from the smaller “nuisance” defects. This approach works for a consumer fab that is only trying to optimize yield, but what about the automotive fab? Recall that yield and reliability issues are caused by the same defects types – yield and reliability defects differ only in their size and/or where they land on the device pattern.2 Therefore, a tool monitoring strategy that leaves the fab blind to smaller defects may be missing the very defects that will be responsible for future reliability issues.

Moreover, it’s important to understand that defects that seem small and inconsequential at one process layer may have a dramatic impact later in the process flow – their impact can be exacerbated by the subsequent process steps. The two SEM images in figure 1 were taken at exactly the same location on the same wafer, but at different steps of the manufacturing process. The image on the left shows a single, small defect that was found on the wafer after a deposition layer. This defect was previously thought to be a nuisance defect with no negative effect on the die pattern or chip performance. The image on the right shows that same deposition defect after metal 1 pattern formation. The presumed nuisance defect has altered the quality of the metal line printed several process steps later. This chip might pass electrical wafer sort, but this type of metal deformity could easily become a reliability issue in the field when activated by automotive environmental stressors.

Figure 1. The left image shows small particle created at a deposition layer. The right image shows the exact same location on the wafer after the metal 1 pattern formation. The metal line defect was caused by the small particle at the prior deposition layer. This type of deformity in the metal line could easily become a reliability issue in the field.

So how does an automotive IC fab determine the smallest defect size that will pose a reliability risk? To start, it is important to understand the impact of different defect sizes on reliability. Consider, for example, the different magnitudes of a line open defect shown in figure 2. A chip that has a pattern structure with a full line open will likely fail at electrical wafer sort and thus does not pose any reliability risk. A chip with a 50% line open – a line that is pinched or otherwise restricted to ~50% of its cross-sectional area – will likely pass electrical wafer sort but poses a significant reliability risk in the field. If this chip is used in a car, environmental conditions such as heat, humidity and vibrations, can cause degradation of this defect to a full line open, resulting in chip failure.

Figure 2. The image on the left shows a full line open, while the right image shows a ~50% line open. The chip on the left will fail at sort (assuming there is no redundancy). The chip on the right may pass electrical wafer sort but is a reliability risk in the field.

As a next step, it is important to understand how different size defects affect a chip’s pattern integrity. More specifically, what is the smallest defect that will result in a line open? What is the smallest defect that will result in a 50% line open?

Figure 3 shows the results of a Monte Carlo simulation that models the impact of different size defects introduced at a BEOL film deposition step. Minimum defect size is plotted on the vertical axis against varying metal layer pitch dimensions. This data corresponds to the metal 1 spacing for the 7nm, 10nm, 14nm and 28nm design nodes, respectively.

The green data points correspond to the smallest defects that will cause a full line open and the orange data points correspond to the smallest defects that will produce a 50% line open (i.e., a potential reliability failure). In each case the smallest defect that will cause a potential reliability failure is 50-75% of the smallest defect that will cause a full line open.

Figure 3. The green data points show the minimum defect size required to cause a full line open at the minimum metal pitch. The orange data points show the minimum defect size needed to cause a 50% line open. The x-axis is the metal 1 spacing for the 7nm (far left data point), 10nm, 14nm and 28nm (far right data point) design nodes.

These modeling results imply that to control for, and reduce, the number of reliability defects present in the process, fabs need to capture smaller defects. Therefore, they require higher sensitivity inspections than what is required for yield optimization. In general, detection of reliability defects requires an inspection sensitivity that is one node ahead of the current design node plan for yield alone. Simply put, a fab’s previous standards for reducing defectivity to optimize yield will not be sufficient to optimize reliability.

Increasing the sensitivities of the tool monitoring inspection recipes, or in some cases, using a more capable inspection system, will find smaller defects and possibly reveal previously hidden signatures of defectivity, as in Figure 4 below. While these signatures may have had a tolerable impact on yield in a consumer fab, they represent an unacceptable risk to reliability for automotive fabs pursuing continuous improvement and Zero Defect standards.

Figure 4: Hidden defect signatures that may impact reliability are often revealed with appropriate tool monitoring sensitivity. Zero Defect standards require corrective action on the process tool contributing these defects.

There are several important unpatterned wafer defect inspection factors for a fab to consider when creating a strategy to improve tool monitoring inspection sensitivity to find the small, reliability-related defects contributed by process tools. First, it is important to recognize that in a mature fab where yields are already high, there is rarely a single process layer or module that will be the “silver bullet” to reducing defectivity adequately to meet reliability improvement goals. Rather, it is sum of small gains across many layers that produce the desired gains in reliability. Because yield and the associated reliability improvements are cumulative across layers, reliability gains achieved through process tool monitoring using unpatterned wafer inspection are best demonstrated using a multi-layer regression model:

Yield = f(Ys)+f(SFS1)+f(SFS2)+ f(SFS3)+ ….. f(SFSN) + error

  • Ys = systematic yield loss (not particles related)
  • SFSx = cumulative Sursfcan unpatterned wafer inspection detected particles for many layers
  • Error = Yield loss mechanisms not detected by Surfscan

This implies that reliability improvements require a fab’s commitment to continuous improvement in defectivity levels across all processes and process modules.

Second, the fab should consider the quality of the bare wafer used for process tool monitoring. Recycling bare wafers increases the surface roughness with each cycle, an attribute known as haze. This haze level is fundamentally noise that affects the inspection system’s ability to differentiate the signal of smaller defects. Variability in haze across the population of test wafers acts as a limit to overall inspection recipe capability, requiring normalization, calibration and haze limits to reduce the impact of this noise source on defect sensitivity.

Next, the fab should ensure that the monitor step closely mimics the process that a production, patterned wafer follows. Small time-saving deviations in the monitor wafer flow to short cut the process may inadvertently skip the causal mechanism of defectivity. Furthermore, an over-reliance on mechanical handling checks alone bypasses the process completely and misses the critical contribution the process plays in particle generation.

When increasing the inspection recipe sensitivity, the fab must co-optimize both the “pre” and “post” inspection together. Often cycling the bare wafer through a process step can “decorate” small pre-existing defects on the wafer that were initially below the detection threshold. Once decorated, the defects now appear bigger and are more easily detected. In an unoptimized “post” inspection, these decorated defects can look like “adders,” leading to a false alarm and inadvertent process tool down time. Optimizing the inspections together maximizes the sensitivity and increases the confidence in the excursion alarms while avoiding time-consuming false alarms.

Lastly, it is important to review and classify the defects found during unpatterned inspection to correlate their relevance to the defects found at the equivalent patterned wafer process step. Only then can the fab be confident that the source of the defects has been isolated and appropriate corrective action has been taken.

To meet the high reliability demands of the automotive industry, IC manufacturers will need to go beyond simply monitoring and controlling the number of yield limiting defects on the wafer. They will need to improve the sensitivity of their tool monitoring inspections to one node smaller than what would historically be considered relevant. Only with this extra sensitivity can they detect and eliminate defects that would otherwise escape the fab and cause premature reliability failures. Additionally, when implementing a tool monitoring strategy, fabs need to carefully consider multiple factors, such as monitor wafer recycling, pre and post inspection sensitivity and the importance of a fab-wide continuous improvement program. With so much riding on automotive semiconductor reliability, increased sensitivity to smaller defects is an essential part of an optimal Zero Defect continuous improvement program.

About the Authors:

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including implementation of strategies for automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

John McCormack is a Senior Director at KLA-Tencor. Barry Saville is Consulting Engineer at KLA-Tencor. John and Barry both have over 25 years of experience in yield improvement and defectivity reduction, working with many IC manufacturers around the world.


  1. Price, Sutherland and Rathert, “Process Watch: The (Automotive) Problem With Semiconductors,” Solid State Technology, January 2018.
  2. Price, Sutherland and Rathert, “Process Watch: Baseline Yield Predicts Baseline Reliability,” Solid State Technology, March 2018.

SEMI, the global industry association serving the electronics manufacturing supply chain, today announced SEMI Works, a comprehensive program to attract, develop and retain the talent critical to the worldwide electronics industry’s continued innovation and growth. The holistic program is designed to improve the industry’s image and provide educational programs for all age groups across the education continuum.

“SEMI has made workforce development and talent advocacy a top priority and dedicated significant resources and expertise to tackle the issue,” said Ajit Manocha, SEMI president and CEO. “As the global industry association anchoring the $2 trillion global electronics industry and representing the end-to-end semiconductor supply chain, SEMI is uniquely positioned to address this problem. We look forward to forming partnerships in leading the way on behalf of our members to build the workforce of the future.”

SEMI Works leverages the SEMI association’s proven track record developing and delivering education and workforce development initiatives as well as its rich history of building public-private partnerships. Under the program, SEMI will establish scalable and sustainable education programs extending from grade-schoolers to adults, offering experiential learning and training programs linked to the skill sets the industry needs most.

“Attracting, training and retaining talent is a major priority for our industry, and we applaud SEMI for taking a lead in workforce development,” said Dan Durn, senior vice president and CFO of Applied Materials, Inc. “SEMI is in a great position to mobilize the right resources and drive the success of this important initiative.”

Leading SEMI Works is Mike Russo, vice president of Global Industry Advocacy at SEMI. Russo brings to bear his more than two decades of talent development experience working with the public and private sectors.

“The global electronics industry’s shortage of high-skilled workers will only become more severe as technology advances,” Russo said. “We need a highly skilled workforce throughout the supply chain to develop new technologies and bring these advances to market. SEMI Works™ will be anchored by both detailed competency models continually updated to support the industry’s rapidly evolving workforce needs and certified education and training aligned to these competencies. This systematic approach will enable us to develop the talent vital to the industry’s prosperity.”

With SEMI Works, SEMI is building on its growing suite of workforce initiatives and involving a consortium of member companies along with its strategic alliances. The program will expand to include public and private sector partners. Organizations interested in contributing to SEMI Works should visit the SEMI Works webpage for program manager contact details.

North America-based manufacturers of semiconductor equipment posted $1.89 billion in billings worldwide in January 2019 (three-month average basis), according to the January Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 10.5 percent lower than the final December 2018 level of $2.10 billion, and is 20.8 percent lower than the January 2018 billings level of $2.37 billion.

“January billings of North American equipment manufacturers declined 10 percent when compared to the prior month,” said Ajit Manocha, president and CEO of SEMI. “Weakening smartphone demand and high inventory levels are eroding capital equipment investments, especially by memory suppliers.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

(3-mo. avg.)
August 2018
September 2018
October 2018
November 2018
December 2018 (final)
January 2019 (prelim)

Source: SEMI (www.semi.org), February 2019

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

The semiconductor industry showed impressive figures in 2017: +21.6% YoY growth to reach about US$ 412 billion. Without any doubt, the industry is entering a new age, where innovation and disruption are the key words. In addition to mobile, Yole Développement (Yole) analysts identified emerging mega-drivers that are step by step changing our world. Big data, AI, 5G, HPC, IoT, smart automotive, industry 4.0, datacenters and more, all mega-trends becoming part of our day to day life, with a direct impact on the semiconductor industry and its supply chain. In its latest report, Status of the Advanced Packaging Industry, Yole predicts an impressive US$39 billion advanced packaging market in 2023 with 7% CAGR.

“The advanced packaging is also driven by the wind of changes, due to the impressive impact of the megatrends,” explained Emilie Jolivet, Division Director, Semiconductor & Software at Yole. “Yole and NCAP China have decided to combine their expertise this year again to propose the Advanced Packaging & System Integration Technology Symposium in Shanghai, prior NEPCON China. This Shanghai edition will be the place to be to understand the industry evolution and measure the impact of the megatrends”.

NCAP CHINA and Yole build an innovative program fully dedicated to the advanced packaging industry: the Advanced Packaging & System Integration Technology Symposium takes place in Shanghai, China, from April 22 to 23, 2019, prior to NEPCON China 2019. During 2 days, all packaging aspects, including Panel Level, Fan-Out, SiP , Advanced Substrates and 3D Technology, will be discussed. A focus on key applications such as AI, HPC, memory, transportation (48V, EV/HEV , embedded die packaging platform, PCB , advanced substrates), 5G and consumer (WLP and Fan-Out platforms) will be at the heart of the conference.

Both partners invite you to meet the leading executives and gain an in-depth understanding of the market evolution! More info.

Mega-trends create huge business opportunities amongst various advanced packaging platforms. Therefore, advanced packaging technologies are just ideal for fulfilling numerous performance and complex heterogeneous integration needs.

“Two advanced packaging roadmaps are foreseen: scaling and functional,” asserts Santosh Kumar, Principal Analyst & Director Packaging, Assembly & Substrates, Yole Korea. “And the semiconductor industry is developing products for both of them. Advanced packaging is seen as a way to increase the value of a semiconductor product, adding functionality, maintaining/increasing performance while lowering cost…”

Both roadmaps developed by the Semiconductor & Software team at Yole, hold more multi-die heterogeneous integration, called SiP, and higher levels of package customization in the future. A variety of SiP solutions is developing in both high and low end, for consumer, performance and specialized applications. Heterogeneous integration has clearly created opportunities for both the substrate and WLP based SiP.

More than that. The advanced packaging supply chain is also involved in this fantastic story. Leading companies, startups, R&D institutes, the worldwide advanced packaging industry is playing the game. In order to expand the business, explore new areas and prepare for future uncertainty, advanced packaging players are moving to different business models:

• Some IDMs such as Intel are entering the foundry business to leverage their front-end technology expertise and create additional revenue stream by utilizing their excess capacity. Samsung, SK Hynix are also part of the playground…
• OEMs , software and service companies are designing their own chips and controlling the supply chain of equipment & materials related to it. Betting on mega-trends such as AI, some OSATs are expanding into the fablite business model.
• Pure play foundries including TSMC, XMC, UMC and SMIC are entering the high-end packaging business to provide turnkey solution to their customers.
• OSATs, such as Amkor Technology, JCET/STATS ChipPAC, ASE, SPIL, Powertech Technology…, are directing considerable efforts in developing advanced wafer level and 3D IC packaging capability to support requirements for scaling & density. OSATs are expanding their testing expertise & traditional pure test players are investing in assembly and packaging capability.
• Substrate manufacturers are penetrating the advanced packaging area with panel-level fan-out packaging and embedded die in organic laminate.

It is a fact. Advanced packaging is at the heart of innovation. Mega-trend applications are bringing new challenges, and leading advanced packaging companies from all over the world will come to exchange ideas on their vision and future perspectives at the Advanced Packaging & System Integration Technology Symposium.

Dr. Cao LiQiang, NCAP’s CEO asserts: “Under the background of China 13th Five-Year Plan and Made in China 2025, local organizations, including NCAP, focus on the core technology development for semiconductor industry and make big progresses. Promoting international communication as well as global cooperation on advanced packaging is the goal shared by Yole and NCAP, and the reason why we insist to organize the activity and make it an annual big event. With good reputations, hot topics and insightful presentations, we firmly believe that 2019 symposium will be a success. Don’t miss the opportunity to learn technology trend and expand your business at China.”

Yole and NCAP have created an unprecedented program to understand the status of the advanced packaging industry and help the companies to be part of the ‘tomorrow’ industry. The Advanced Packaging & System Integration Technology Symposium is unique.

The semiconductor business is defined by rapid technological changes and the need to maintain high levels of investment in research and development for new materials, innovative manufacturing processes for increasingly complex chip designs, and advanced IC packaging technologies.

However, since the 1980s, the long-term trend has been toward a slowdown in the annual growth rate of research and development expenditures according to data presented in the new, 2019 edition of IC Insights’ McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry (released in January 2019). Consolidation in the semiconductor industry has been a big factor contributing to lower growth rates for R&D expenditures so far this decade. In the most recent five-year span from 2013-2018, semiconductor R&D spending grew by CAGR of 3.6% per year, essentially unchanged from the 3.3% experienced from 2008-2013 (Figure 1).

Figure 1

IC Insights expects new challenges such as three-dimensional (3D) die-stacking technologies, growing complexities in end-use applications, and other significant manufacturing barriers to raise semiconductor R&D spending to a slightly higher growth rate of 5.5% per year in the 2018-2023 forecast period.

R&D spending trends discussed here cover expenditures by integrated device manufacturers (IDMs), fabless chip suppliers, and pure-play wafer foundries and do not include other companies and organizations involved in semiconductor-related technologies, such as production equipment and materials suppliers, packaging and test service providers, universities, government-funded labs, and industry cooperatives, such as IMEC in Belgium, the CAE-Leti Institute in France, the Industrial Technology Research Institute (ITRI) in Taiwan, and the U.S.-based Sematech consortium, which was merged into the State University of New York (SUNY) Polytechnic Institute in 2015.

With the value of more than 90 merger and acquisition agreements topping $250 billion since 2015, tremendous consolidation has been underway among semiconductor suppliers—many of them major IC companies—which have been cutting costs by hundreds of millions of dollars and leveraging “synergies,” meaning the elimination of overlapping expenditures (e.g., jobs, facilities, and R&D activities) in an attempt to achieve higher levels of productivity and greater profits. After rising just 1% in 2015 and 2016, total semiconductor R&D spending grew 6% in 2017 and increased 7% in 2018 to reach a new record- high level of $64.6 billion.

During the last 40 years (1978-2018), R&D expenditures have increased at a compound annual growth rate of 14.5%, slightly higher than the total semiconductor revenue CAGR of 12.0%. Since the year 2000, semiconductor R&D spending as a percent of worldwide sales has exceeded the 40-year historical average of 14.5% in all but four years (2000, 2010, 2017, and 2018). In these four years, lower R&D-to-sales ratios had more to do with the strength of revenue growth than weakness in research and development spending.

Annual semiconductor unit shipments, including integrated circuits and optoelectronics, sensors, and discrete (O-S-D) devices grew 10% in 2018 and surpassed the one trillion unit mark for the first time, based on data presented in the new, 2019 edition of IC Insights’ McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry. As shown in Figure 1, semiconductor unit shipments climbed to 1,068.2 billion units in 2018 and are expected to climb to 1,142.6 billion in 2019, which equates to 7% growth for the year.  Starting in 1978 with 32.6 billion units and going through 2019, the compound annual growth rate for semiconductor units is forecast to be 9.1%, a very impressive growth figure over 40 years, given the cyclical and often volatile nature of the semiconductor industry.

Figure 1

Over the span of just four years (2004-2007), semiconductor shipments broke through the 400-, 500-, and 600-billion unit levels before the global financial meltdown caused a big decline in semiconductor unit shipments in 2008 and 2009.  Unit growth rebounded sharply with 25% growth in 2010, which saw semiconductor shipments surpass 700 billion devices. Another strong increase in 2017 (12% growth) lifted semiconductor unit shipments beyond the 900-billion level before the one trillion mark was achieved in 2018.

The largest annual increase in semiconductor unit growth during the timespan shown was 34% in 1984, and the biggest decline was 19% in 2001 following the dot-com bust.  The global financial meltdown and ensuing recession caused semiconductor shipments to fall in both 2008 and 2009; the only time that the industry experienced consecutive years in which unit shipments declined.  The 25% increase in 2010 was the second-highest growth rate across the time span.

The percentage split of total semiconductor shipments is forecast to remain heavily weighted toward O-S-D devices in 2019 (Figure 2).  O-S-D devices are forecast to account for 70% of total semiconductor units compared to 30% for ICs.  This percentage split has remained fairly steady over the years.  In 1980, O-S-D devices accounted for 78% of semiconductor units and ICs represented 22%.  Many of the semiconductor categories forecast to have the strongest unit growth rates in 2019 are those that are essential building-blocks for smartphones, automotive electronics systems, and devices that are used in computing systems essential to artificial intelligence, “big data,” and deep learning applications.

Figure 2


By Ajit Manocha

Last year the industry posted another remarkable double-digit revenue growth year. IC shipments eclipsed one trillion units for the first time and continued to enable an ever-expanding array of silicon intensive-applications.

2018 was also a pivotal year of transformation at SEMI. Setting our sights firmly on building more value for SEMI members, we doubled down on priorities I established this time last year. We advocated intensively on global trade policies, industry talent needs, and critical environment, health and safety (EHS) concerns. To underpin our efforts around talent, we took the bold step to reinvigorate the industry’s identity with a dynamic image campaign. Above all, we targeted critical industry-wide issues to help us realize the ambition of becoming a trillion-dollar industry in the next decade.

Workforce Development

Redefining our approach to talent development in 2018 was and remains a top priority. A diverse, highly skilled workforce is crucial to the industry’s ability to innovate. Last year we ramped up a number of  SEMI High Tech U (HTU) programs to inspire young people and attract them to careers in high-tech manufacturing. To date, more than 130,000 students have been touched by HTU – through student or teacher programs.

Over the past year, we designed a new university outreach program and established partnerships with 100 institutions. We established Workforce Pavilions at SEMICON events in Southeast Asia, the U.S., Taiwan, Europe and Japan for students to explore career opportunities and meet with recruiters. We thrilled at seeing sponsors hire young talent at SEMI events. This year, all SEMICONs worldwide will feature Workforce Pavilions.

SEMI also formalized its commitment to Diversity and Inclusion (D&I) with the establishment of a D&I council to shape new programs including the recently launched Spotlight on SEMI Women. To localize and fully optimize our D&I programs, we established regional workforce councils in every region we serve.

We unveiled the SEMI Mentoring Program to support students and young professionals on this journey by facilitating one-on-one mentoring relationships with industry professionals. Hundreds of mentees have enrolled. But we still need more mentors.  I urge you to join the program.

During the year, SEMI also expanded its workforce staff and developed a comprehensive workforce strategy with programs that engage students as early as elementary school and inspires them through high school and college. The program provides pathways to professional careers, building a pipeline to fill the short-term and long-term talent needs of the industry.

Industry Image Campaign

As we developed the comprehensive workforce development program, we knew we had to refresh the industry’s image and appeal to the next generation through contemporary media and communications channels. So we recently launched a bold, innovative campaign to raise industry awareness and attract students and recent graduates to careers in semiconductor manufacturing.

Our You’re Welcome campaign is a novel, creative approach that blends entertainment, media and storytelling to excite students about the industry. The campaign went viral immediately and within weeks had more than 5.5 million social media impressions and 2.3 million video views.

Trade Policy Advocacy

Rising trade tensions between the U.S. and China catapulted global trade policy to the forefront of industry concerns in 2018. Since the tariffs have taken force, semiconductor companies have faced higher costs, greater uncertainty, and difficulty selling products abroad. The tariffs have forced many SEMI member companies to pause or rethink their investment strategies.

SEMI quickly engaged U.S. policymakers and provided resources for SEMI members. We formed a member trade task force, staged trade compliance seminars in China, and convened meetings with over 110 U.S. congressional, agency and administration officials, and provided testimony on the importance of the free trade to the industry.

SEMI continues to educate policymakers about the critical importance of free and fair trade, open markets, and respect and enforcement of IP for all players in the global electronics manufacturing supply chain. As part of this initiative, we distributed “10 Principles for the Global Semiconductor Supply Chain in Modern Trade Agreements” and encouraged their adoption in various trade negotiations. These principles outline the primary considerations for balanced trade rules that benefit SEMI members around the world, strengthen innovation and perpetuate the societal benefits of affordable microelectronics.

Environment, Health and Safety

Environmental regulations are proliferating globally even as advanced semiconductor manufacturing technology relies increasingly on a host of new materials. With dozens of new fabs and fab line upgrades, our industry must align on best practices, sensibly respond to materials restrictions, and renew efforts toward sustainable manufacturing.

That’s why the revitalization of SEMI EHS efforts became another priority in 2018. Two months ago, we hosted the inaugural EHS Summit at SEMI Headquarters. Fully, 70 EHS professionals and company executives met to form the basis for the future SEMI EHS program.

The Year Ahead

Despite a softening in the market, compounded by Apple’s first-ever announcement of a revenue decline in 16 years, a geopolitical whirlwind on trade and an extended shutdown of much of the U.S. government, the future is bright.

At SEMI’s annual Industry Strategy Symposium (ISS 2019) in Half Moon Bay, Calif. in early January,  the sense of optimism was palpable. In her keynote address, Dr. Ann Kelleher, Sr. VP and General Manager, Technology and Manufacturing Group, at Intel, observed that data is powering the fourth industry revolution and the expansion of compute. With customers expecting continual improvements in applications, Kelleher highlighted the tremendous opportunity for the chip industry to meet these expectations.

At ISS 2019, we announced a Memorandum of Understand between SEMI and imec. The MOU will enable us to accelerate our members’ engagement in SEMI’s Smart vertical market platforms, in particular Smart MedTech and Smart Transportation. Our partnership with imec will also allow us to boost SEMI Standards activities in non-CMOS technologies, deepen technology roadmap efforts and augment our SEMI Think Tank initiative in thought leadership at a global level.

Over the course of this coming year, will we begin our global rollout of key building blocks of our comprehensive workforce development program to engage schoolchildren as young as 10 and learners all the way to veterans who return to the workforce. We are now able, with the invaluable help of our Workforce Development Council and the passionate engagement of many SEMI member companies, to offer a solution to the talent crisis in our industry.

We will continue to be the leading voice for our members and the end-to-end semiconductor supply chain across Talent, Trade, Tax and Technology as we work to ensure free, fair trade that protects IP while preserving vital access to markets to grow the supply chain.

Vertical Market Platforms

Our vertical market platforms are an important part of this growth. For example, in Smart MedTech, SEMI looks forward to working with the Nano-Bio Materials Consortium to advance human monitoring technology for telemedicine and digital health after winning $7 million to fund the renewed program. In Smart Transportation, we will leverage the Global Automotive Advisory Council (GAAC) we formed last year to represent the full automotive supply chain and the Smart Transportation and Smart Automotive forums featured at all our SEMICON events to enable the industry to identify and seize opportunities in autonomous driving.

At ISS 2019, Sujeet Chand of Rockwell Automation noted that “digitization will grow faster in the next 10 years than it did in the past 50,” a trend calling for semiconductor fab architectures that transform data into business value. We will continue to bring the industry together at our Smart Manufacturing venues to help uncover ways to deploy deep learning, edge computing and other Smart technologies to deliver this value and meet the challenges of automation as artificial intelligence’s (AI) sprawling influence reshapes industries including manufacturing.

I am filled with optimism and thrilled about the opportunities I see on the horizon for our members as we build on our 2018 accomplishments to enable your prosperity in 2019 and beyond. My heartfelt thanks to all of you for your participation in our programs and events.

I look forward to another successful year as we connect, collaborate and innovate together!

Ajit Manocha is president and CEO of SEMI. 

By Rohit Sharma

Constant coverage of an invigorating topic like machine intelligence in the media often urges us to consider its use in EDA technology. As is often the case, there are many myths and falsehoods that consume our time and effort when trying to apply machine intelligence to EDA. This article aims to uncover the myths and to provide helpful advice on applying machine intelligence to your EDA project or product.

Value Proposition

First, there needs to be a clear value proposition for adding machine intelligence to an EDA product. Using machine intelligence to create a me-too product adds no value. EDA customers are too busy to understand or care about an EDA tool’s underlying technology. They just want to use the tool and get results. If the tool delivers value, if it delivers tangible benefits, then they’ll use it. Otherwise, they won’t.

Currently, EDA tool developers are already experimenting with AI and machine intelligence without considering this fundamental truth – without a higher-end objective. AI must deliver something better or new, whether a speed advantage, a performance advantage, new features, new insights, or perhaps even something pleasantly surprising. Before you write a single line of AI-enhanced code, you need to clearly understand how AI will enhance the product. What is the value proposition?

Use Model

There’s a major barrier to customer adoption of AI and machine intelligence technology for EDA tools: EDA users are averse to make decisions based on probabilistic results. Instead, half a century of EDA tool use has conditioned them to expect deterministic outcomes from their tools.

Back in 2003, a prominent visionary and EDA investor was quoted in an interview, saying: “If I open my eyes five years from now, all static analysis in VLSI will be statistical.” Many EDA luminaries have been proven wrong over time for betting that EDA users will accept statistical results. As enthusiastic as I am about using machine intelligence to improve EDA tools, I must urge caution based on the history of EDA failures that employed a probabilistic use model. Decision-makers and EDA tool users want to see deterministic answers to questions about yield or slack, not probabilistic ones.

Our experiences at Paripath in developing the PASER (Paripath Accelerated Simulation Environment) tool also bear this out. We discovered that delivering results 50x faster but with 92% accuracy was simply not good enough for end users. EDA users only started to use PASER when its answers became 98+% accurate. To be adopted in the production flow, the tool had to deliver 99% accuracy.

Data Engineering

There are specific ways to achieve these accuracy goals. The first is data engineering. Machine intelligence is a new approach to EDA tool development and it needs to be trained on a data set. If the data is poor or incomplete, training will create an inaccurate model. Fundamental software-development rules still apply. Garbage in, garbage out.

Without good training data, there’s no way for you to build good neural-network models. If you train a model with garbage data, you’ll get a garbage model. You must cleanse the data before you use it for training. Otherwise, the model will draw inaccurate conclusions and customers will not use your tool. The model is not to blame here. The model’s not wrong. The problem lies in poor data engineering, poor data cleansing, and a lack of discipline to prepare input data.

High Dimensionality

Next, machine intelligence has a unique ability to quickly solve problems of high dimensionality. Pure EDA problems often have high dimensionality. Over the years, EDA developers have perfected the art of segmenting the problems into sequencing solutions with lower dimension. Machine intelligence technology can handle problems with thousands of dimensions, but you need to be careful when tackling problems that have high dimensionality. Too many dimensions can produce confused or inaccurate results with AI and deep-learning technology.

It helps to visualize the problem and to analyze the data set before using the data to train an AI-enhanced EDA tool. Several visualization methods can help. For example, t-SNE (t-Distributed Stochastic Neighbor Embedding) lets you reduce a data set’s dimensionality from a very large number to a much lower number. Figure 1 shows a high-dimension dataset with a dimensionality of 2000, which has been reduced to a low dimensionality of 3.

Figure 1: Visualizing the Data Set with Lower Dimensionality

Reducing the dimensionality of a data set to 3 using t-SNE and visualization allows you to quickly see whether the data set defines an easy or a difficult problem. If the problem is difficult, you’ll likely need to lower the problem’s and the data set’s dimensionality before using the data to train a neural network.

Technology Selection

One factor that determines whether it will be easy or difficult to incorporate machine intelligence into your EDA tool is your choice of AI development tools. AI researchers have developed a long list of frameworks, libraries, and languages that they use to develop AI and machine-learning software. Frameworks and libraries such as TensorFlow, Caffe and MXNet are most popular for developing deep-learning models.

However, these tools are not yet popular with the EDA development community. The languages of choice in the EDA community are traditionally C and C++ for development and Tcl for prototyping and creating user interfaces. The rest of the software world has moved on to newer development languages such as Python, Java, R, and such. Moreover, machine-learning development segments into two distinct processes: training (i.e. generating the model) and inference (i.e. using the model).

Another question to consider is where to generate the model – at the vendor site or the customer site?

Consequently, fitting AI and deep-learning development into EDA development environments can feel like fitting a square peg into a round hole. You may need to create corners in your hole.

EDA is a very small player in the overall software market. Relatively few software developers are familiar with writing EDA tools. It’s best to select AI and deep-learning development tools that can provide some sort of interface that’s compatible with EDA’s development tools of choice. Some AI frameworks have lower-level C and C++ interface layers that provide a familiar entry point for experienced EDA developers.

At Paripath, we chose TensorFlow for exactly this reason. TensorFlow has a lower-level C/C++ interface. Although the resulting development path becomes a longer one using this approach, it’s a more familiar path for EDA developers and therefore it’s a path that can ultimately lead your EDA development team to success. An elaborate study of comparing these frameworks has been published in the book Machine Intelligence in Design Automation.

Integration into Legacy Systems

When you understand the value that you expect machine intelligence to add to your new EDA tool, when you’ve cleansed and then analyzed the data set, and when you have selected an appropriate set of development tools, you’re finally ready to add machine intelligence to your EDA development. There are two use models for AI-enhanced EDA tools. The first uses a trained model to guide the EDA tool’s decision-making. In this use case, the trained neural network doesn’t change. The software’s accuracy doesn’t improve with use unless the company that developed the EDA tool retrains the underlying neural network. This use case follows the familiar, existing use case associated with EDA tools developed using deterministic algorithms.

For the second use case, the end user is able to retrain the underlying neural network, which allows the EDA tool to produce better, more accurate results over time. This use case produces a win/win situation because end users are able to hone their tools and improve them over time, without help from the EDA tool vendor’s application engineers. If the retrained models are also sent back to the EDA developer for incorporation into newer versions of the tool, all users benefit from other users’ training data.

It’s not clear how you’d support this second use case in the current EDA business environment where most data sets are proprietary and are carefully guarded. Most large EDA tool customers want to keep their data in house under tight control. Even with this somewhat restrictive situation, however, EDA tools benefit from the incorporation of machine intelligence because each EDA tool customer can customize the tool and improve its results.

Machine intelligence has much to add to EDA tools’ capabilities. Only time will tell if the customers want and will accept these new capabilities.

Rohit Sharma, founder and CEO of Paripath Inc., is an engineer, author and entrepreneur. He has published many papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including machine learning, analysis, characterization, and modeling. It led him to architect guna – an advanced characterization software for modern nodes. 

Sharma has written a book titled “Machine Intelligence for Design Automation.” You can download code examples and other information here.

This originally appeared on the SEMI blog.

IC Insights is in the process of completing its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published later this month.  Among the semiconductor industry data included in the new 400+ page report is an analysis of semiconductor merger and acquisition agreements.

The historic flood of merger and acquisition agreements that swept through the semiconductor industry in 2015 and 2016 slowed significantly in 2017 and then eased back further in 2018, but the total value of M&A deals reached in the last year was still nearly more than twice the annual average during the first half of this decade.  Acquisition agreements reached in 2018 for semiconductor companies, business units, product lines, and related assets had a combined value of $23.2 billion compared to $28.1 billion in 2017, based on data compiled by IC Insights.  The values of M&A deals struck in these years were significantly less than the record-high $107.3 billion set in 2015 (Figure 1).

Figure 1

The original 2016 M&A total of $100.4 billion was lowered by $41.1 billion to $59.3 billion because several major acquisition agreements were not completed, including the largest proposed deal ever in semiconductor history—Qualcomm’s planned purchase of NXP Semiconductor for $39 billion, which was raised to $44 billion before being canceled in July 2018.  Prior to the explosion of semiconductor acquisitions that erupted four years ago, M&A agreements in the chip industry had a total annual average value of $12.6 billion in the 2010-2014 timeperiod.

The two largest acquisition agreements in 2018 accounted for about 65% of the M&A total in the year.  In March 2018, fabless mixed-signal IC and power discrete semiconductor supplier Microsemi agreed to be acquired by Microchip Technology for $8.35 billion in cash.  Microchip said the purchase of Microsemi would boost its position in computing, communications, and wireless systems applications.  The transaction was completed in May 2018.  Fabless mixed-signal IC supplier Integrated Device Technology (IDT) agreed in September 2018 to be purchased by Renesas Electronics for $6.7 billion in cash.  Renesas believes the IDT acquisition will strengthen its position in automotive ICs for advanced driver-assistance systems and autonomous vehicles.  The IDT purchase is expected to be completed by June 2019.

Just two other semiconductor acquisition announcements in 2018 had values of more than $1 billion.  In October 2018, memory maker Micron Technology said it would exercise an option to acquire full ownership of its IM Flash Technology joint venture from Intel for about $1.5 billion in cash. Micron has started the process of buying Intel’s non-controlling interest in the non-volatile memory manufacturing and development joint venture, located in Lehi, Utah.  The transaction is expected to be completed in 2H19.  In September 2018, China’s largest contract manufacturer of smartphones, Wingtech Technology, began acquiring shares of Nexperia, a Dutch-based supplier of standard logic and discrete semiconductors that was spun out of NXP in 2017 with the financial backing of Chinese investors.   Wingtech launched two rounds of share purchases from the Chinese owners of Nexperia with a combined value of nearly $3.8 billion.  The company hopes to take majority ownership of Nexperia (about 76% of the shares) in 2019.

IC Insights is in the process of completing its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published later this month.  Among the semiconductor industry data included in the new 400+ page report is an in-depth analysis of semiconductor capital spending.

The semiconductor industry is expected to allocate the largest portion of its capex spending for flash memory again in 2019, marking the third consecutive year that flash has led all other segments in spending (Figure 1).  Flash memory trailed the foundry segment in capex in 2016, but took an extra-large jump in 2017, growing 92% to $27.6 billion and increased another 16% to $31.9 billion in 2018 as manufacturers expanded and upgraded their production lines for 3D NAND to meet growing demand.  With much of the expansion now completed or expected to be wrapped up in 2019, flash capex is forecast to decline 18% this year to $26.0 billion, which still is a very healthy spending level.

Figure 1

•    In 2018, SK Hynix completed and opened M15 its new wafer fab facility in Cheongju, South Korea.  First devices produced from the factory were 72-layer 3D NAND flash.

•    Micron allocated significant resources to upgrade its two existing flash fabs in Singapore and broke ground on construction of a third NAND wafer fab there.

•    Toshiba Memory completed construction of a new 300mm wafer plant (Fab 6) at its Yokkaichi site in 1H18.  Operations at Phase 1 of the facility are expected to begin in early 2019.  Also, Toshiba announced that its next flash memory fab after Fab 6 would be located in Kitakami, Iwate.  The company broke ground on this fab in July 2018.

•    XMC/Yangtze River Storage Technology (YMTC), which is owned by Tsinghua Unigroup, completed construction of its new fab, installed equipment, and began small-volume production of 32-layer 3D NAND flash.

•    Samsung and all of the other “legacy” flash suppliers are well aware of the big plans that China has to be a player in the 3D NAND flash market.  Samsung will continue to invest heavily to stay far ahead of existing competitors or new startups and maintain its competitive edge against any who think they can wrestle marketshare away.  Samsung spent $13.0 billion on flash capex in 2017 and $9.0 billion in 2018, accounting for 28% of the total $31.9 billion in flash memory capital spending last year.  IC Insights estimates Samsung will spend another $7.0 billion for flash capex in 2019.