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London, UK and San Jose, California – Dialog Semiconductor and Atmel Corporation announced today that Dialog has agreed to acquire Atmel in a cash and stock transaction for total consideration of approximately $4.6 billion. The acquisition creates a global leader in both Power Management (defined as power management solutions for mobile platforms including smartphones, tablets, portable PCs and wearable-type devices) and Embedded Processing solutions. The transaction results in a company that supports Mobile Power, IoT and Automotive customers. The combined company will address a market opportunity of approximately $20 billion by 2019.

Dialog will complement its position in Power Management ICs with a portfolio of proprietary and ARM (R) based Microcontrollers in addition to high performance ICs for Connectivity, Touch and Security. Dialog will also leverage Atmel’s established sales channels to diversify its customer base. Through realized synergies, the combination could deliver an improved operating model and enable new revenue growth opportunities.

“The rationale for the transaction we are proposing today is clear – and the potential this combination holds is exciting. By bringing together our technologies, world-class talent and broad distribution channels we will create a new, powerful force in the semiconductor space. Our new, enlarged company will be a diversified, high-growth market leader in Mobile Power, IoT and Automotive. We firmly believe that by combining Power Management, Microcontrollers, Connectivity and Security technologies, we will create a strong platform for innovation and growth in the large and attractive market segments we serve. This is an important and proud milestone in the evolution of our Dialog story,” said Jalal Bagherli, Dialog Chief Executive Officer.

“This transaction combines two successful companies and will create significant value for Atmel and Dialog shareholders, customers and employees. Adding Dialog’s world-class capabilities in Power Management with Atmel’s keen focus on Microcontrollers, Connectivity and Security will enable Dialog to more effectively target high-growth applications within the Mobile, IoT and Automotive markets,” said Steven Laub, Atmel President and Chief Executive Officer.

The transaction is expected to close in the first quarter of the 2016 calendar year. In 2017, the first full year following closing, the transaction is expected to be accretive to Dialog’s underlying earnings. Dialog anticipates achieving projected annual cost savings of $150 million within two years. The purchase price implies a total equity value for Atmel of approximately $4.6 billion and a total enterprise value of approximately $4.4 billion after deduction of Atmel’s net cash. Dialog expects to continue to have a strong cash flow generation profile and have the ability to substantially pay down the transaction debt approximately three years after closing.

The transaction has been unanimously approved by the boards of directors of both companies and is subject to regulatory approvals in various jurisdictions and customary closing conditions, as well as the approval of Dialog and Atmel shareholders. Jalal Bagherli will continue to be the Chief Executive Officer and Executive Board Director of Dialog. Two members of Atmel’s existing Board will join Dialog’s Board following closing. The transaction is not subject to a financing condition.

By Christian Gregor Dieseldorff, Industry Research & Statistics, SEMI (September 8, 2014)

The general consensus for the semiconductor industry is for this year’s positive trend to continue into 2015 as both revenue growth and unit shipment growth are expected to be in the mid- to high- single digit range. SEMI just published the World Fab Forecast report at the end of August, listing major investments for 216 facilities in 2014 and over 200 projects in 2015.  The report predicts growth of 21% for Front End fab equipment spending in 2014 (including new, used, and in-house), for total spending of US$34.9 billion, with current scenarios ranging from 19% to 24%.

Front end fab equipment spending is projected to grow another 20% in 2015 to $42 billion.  According to the SEMI World Fab Forecast data, this means that 2015 spending could mark a historical record high, surpassing the previous peak years of 2007 ($39 billion) and 2011 ($40 billion).

About 90% of all equipment spending is for 300mm fabs, and, interestingly, the report also shows increased fab equipment spending for 200mm facilities, growing by 10% in 2014.  Equipment spending for wafer sizes less than 200mm is also expected to grow by a healthy 12% in 2015 which includes LEDs and MEMS fabs.

According to the World Fab Forecast, the five regions spending the most in 2014 will be Taiwan ($9.7 billion), Americas ($7.8 billion), Korea ($6.8 billion), China ($4.6 billion), and Japan ($1.9 billion). In 2015, the same regions will lead: Taiwan ($12 billion), Korea ($8 billion), Americas ($7.9 billion), China ($5 billion), and Japan ($4.2 billion). Spending in Europe is expected to nearly double to $3.8 billion.

Seven companies are expected to spend $2 billion or more in 2014, representing almost 80% of all fab equipment spending for Front End facilities. A similar pattern will prevail in 2015.

Worldwide installed capacity falls below 3% mark


Figure 1 illustrates fab equipment spending since 2003 and the change of installed capacity (excluding Discretes and LEDs).

As Figure 1 illustrates, before the last economic downturn, most equipment spending was for adding new capacity. The World Fab Forecast report shows that in 2010 and 2011, fab equipment spending growth rates increased dramatically, but installed capacity grew by only 7% in both years. Then in 2012 and 2013, growth for installed capacity sagged even further with only 2% and even less growth. Previously, growth rates less than 2% have been observed only during severe economic downturns (2001 and 2009).

Industry segments, such as foundries, see continuous capacity expansion, though other segments show much lower growth — thus pulling down the total global growth rate for installed capacity to below the 3% mark. Although spending on equipment, some leading-edge product segments experience a loss of fab capacity and, looking closer at this phenomenon, two major trends are observed.

First, coming out of the 2009 downturn, SEMI reports that companies are spending much more on upgrading existing fabs.  From 2005-2008, yearly average spending on upgrading technology was about $6 billion compared to the period of 2011-2015 when the yearly average increased to $14 billion for upgrading existing fabs.  Second, leading-edge fabs experience a loss of capacity when transitioning to leading-edge technology. This is largely observed with nodes below 30/28nm with the increasing complexity and process steps resulting in a -8% to -15% reduction in capacity for fabs.

In addition to foundries, the World Fab Forecast report captures capacities across all industry segments as well as System LSI, Analog, Power, MEMS, LED, Memory and Logic/MPUs. The Logic/MPU sector is also expected to see some positive capacity expansion for 2014 and 2015. Flash capacity is expected to increase by 4% in 2014. Although we see more DRAM capacity coming online, DRAM is now slowly coming out of declining territory with -3% in 2014 and reaching close to zero by end of 2015.

More DRAM capacity?

Over the past three to four years, some major players (such as Samsung, Micron, and SK Hynix) have switched fabs from DRAM to System LSI or Flash.  In addition, other companies stopped DRAM production of some fabs completely, contributing to declining DRAM capacity. Equipment spending levels for DRAM fabs in 2012 and 2013 were near the $4 billion mark annually and are described by some industry observers as being at “maintenance level.”  Increased spending is expected for DRAM in 2014 and 2015, yet although more capacity is being added — the rates are still negative until the end of 2015.  See Figure 2.

Figure 2: Fab equipment spending is compared to the change rate of capacity for DRAM.

Figure 2: Fab equipment spending is compared to the change rate of capacity for DRAM.

As discussed above, SEMI reports that leading-edge DRAM fabs undergo a double-digit capacity loss when upgraded due to an increase in processing steps and complexity. Since the end of last year, Samsung is in the process of adding additional DRAM capacity with two new lines — Line 16 (ramping up this year) and its new Line 17 (the first new DRAM fab ramped since the last economic downturn). In addition SK Hynix is ramping up its M14 DRAM line in 2016. We expect the impact to overall DRAM capacity expansion to occur in 2015 when this fab begins to ramp up. Even if this fab ramps to about half of its potential, the change rate for installed DRAM capacity would still not be positive by end of next year.

Over $6 billion for Fab construction projects

The SEMI World Fab Forecast also provides detailed data about fab construction projects underway. Construction spending is expected to total $6.7 billion in 2014 and over $5 billion in 2015.  Leading regions in spending for 2014 will be Taiwan, Americas, and Korea.  In 2015, the highest spending will be seen in Europe/Mideast, followed by Taiwan and Japan.

Only five companies show strong spending numbers for new fabs or refurbishing existing fabs. Their combined fab construction spending accounts for 88% of all worldwide fab construction spending for Front End facilities.

In 2014, the SEMI report shows 16 new fab construction projects (six alone for 300mm) and 10 fab construction project in 2015 (four for 300mm). Most construction spending in 2014 is for Foundries ($3.1 billion) followed by Memory ($2.5 billion) and Logic. In 2015, Memory will have most spending with ($2.3 billion) closely followed by Foundries ($2.2 billion).

The report lists currently 1150 facilities with 68 future facilities with various probabilities which have started or will start volume production in 2014 or later. See Figure 3.

Figure 3: Count of known facilities (Volume fabs to R&D) in the World Fab Forecast report with various probabilities which are expected to start production in 2014 to 2020.

Figure 3: Count of known facilities (Volume fabs to R&D) in the World Fab Forecast report with various probabilities which are expected to start production in 2014 to 2020.

As it looks right now, SEMI reports that the outlook is positive for 2014 for the chip-making industry compared to the previous few years and the outlook for 2015 also remains healthy.  However, given the current investment trends for spending at the advanced technology nodes and the decline in construction related activity, we continue to expect worldwide capacity expansion to remain in the low-single digits in the next three to five years.

SEMI World Fab Forecast Report

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter. These tools are invaluable for understanding how the semiconductor manufacturing will look in 2014 and 2015, and learning more about capex for construction projects, fab equipping, technology levels, and products.

The SEMI Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data tracks only new equipment for fabs and test and assembly and packaging houses.  The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment. Also check out the Opto/LED Fab Forecast. Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats


Capital equipment suppliers must provide advanced analytical systems that leverage data generated by their tools to help their fab customers address the challenges of Big Data and advanced analytics. 

BY TOM MARIANO, Foliage, Burlington, MA 

We live in a highly-connected world. Powerful intelligent devices for personal and home use are pervasive and proliferating at an accel- erated rate and will number in the tens of billions in the years to come. These devices are connected to powerful back-end software creating intelligent systems. The semiconductor industry is a major enabler of these intelligent systems. The industry’s drive to adhere to Moore’s Law has resulted in extremely low-cost memory, tremendous computing power and high-speed connectivity, in packages that are low cost and have low power consumption.

These device-level advances when combined with innovations in information technology such as Cloud computing, Big Data and advanced analytics are at the core of intelligent systems that impact our daily lives. Glancing at my phone right now, I see iTunes, YouTube, LinkedIn and my home and work email—all evidence of Cloud computing. Big Data and advanced analytics are widely used for such things as targeted advertising, insurance and credit underwriting, fraud detection, healthcare research, legal discovery, social network analysis and many other areas that impact our lives. Cities around the world, from Da Nang to Fort Lauderdale are applying technologies such as advanced data and analytical tools, cloud-based services and integrated wireless services to make life easier for everyone.

In the manufacturing industry, there is a parallel revolution also leveraging the same advanced information technologies – intelligent manufacturing. The adoption of robotics and automation in manufacturing is increasing precipitously. The use of 3D printing is exploding. Manufacturing machines are becoming more and more intelligent and warehouse automation is rapidly expanding. Intelligent manufacturing systems are dependent on data—data that is shared and acted upon at all levels.

This is leading to changes on the data side as supply chains are being automatically linked for improved tracking and coordination. Advanced analytics are enabling real-time decision making on the factory floor while tool diagnostics are often happening remotely and sometimes automatically. The semiconductor industry has led other manufacturing sectors in the adoption of highly automated, intelligent manufacturing, but is lagging in the application of new information technologies.

Out in front

The need for smaller feature sizes and more aggressive cleanliness and particle-count metrics is the very nature of the semiconductor industry. The accuracy and precision requirements of this complex micro-fabrication process has always necessitated its isolation from direct human intervention. This necessity to isolate semiconductor wafer processing from humans and the drive to adhere to Moore’s Law has pushed advanced technology into the semiconductor manufacturing process resulting in significant progress in automation and optimization of process and production. Clean processing has driven the proliferation of wafer-handling automation within process tools. Wafer-handling robot arms in vacuum and atmospheric tools are standard today. Meanwhile, Moore’s Law played the primary role in wafer size increases and the automation that is present outside of the process tools.

Starting in the 200mm generation, mini-environments (i.e., SMIF pods) as a means to isolate wafers from particles during inter-tool transport became standard. The standard carrier with twenty-five wafers, and its resulting high weight along with the increased fab throughput demands driven by Moore’s Law, led to the propa- gation of inter-bay automated material handling systems (AMHS). The movement of wafers from one processing bay to the next became automated. This trend continued in the 300mm generation with larger and heavier standard carriers (i.e., FOUPs). And with this generation came standardized intra-bay AMHS. Process tool to process tool delivery of wafers was automated as a result. Fully-automated, chamber-to-chamber automation in the semiconductor industry (at least for front-end processing) is decades ahead of other discrete manufacturing industries. In recent years, there’s been an acceleration of robotics within non-semiconductor sectors, but most of these industries are only scratching the surface compared to the semiconductor industry concerning material handling automation.

The semiconductor manufacturing process has also made major advances in data automation. The manufacture of computer chips is extremely complex requiring hundreds of process steps, each affecting change to the silicon wafers at a microscopic level. Also complicating the process is the need for producing multiple products in the same fab with overlapping, but also divergent process steps. This complexity drove the need and proliferation of manufacturing execution systems (MES) in semiconductor processing. Process tool data connections, so-called tool automation is also commonplace, enabling automatic recipe download and tool configuration, remote control and automated data collection. Advanced Process Control (APC) is widely used to improve yield.

And finally, due to the re-entrant repetitive WIP flow required by wafer processing, sophisticated WIP scheduling and dispatching systems exist to optimize, as much as possible, fab throughput and cycle time in pursuit of Moore’s Law. When it comes to data, semiconductor manufacturing is out in front of other discrete manufacturing industries – by far it seems. In the semi industry, the combination of one hundred percent of processing tools connected and automated with metrology feedback loops via APC is not something you see in other discrete manufacturing sectors.

But lagging behind

Recent actions by several large well-known companies emphasize the escalating trend toward intelligent manufacturing. Apple, moving toward fully automated production lines in the U.S., allocated $11B to robotics and automation technology. General Electric announced a $3B investment in the “Industrial Internet of Things.” Google acquired eight robotics companies in 2013. And, Amazon bought Kiva Systems, a warehouse automation company for $750M. Similar actions echoed by thousands of less well-known companies, albeit predominantly on a smaller scale, are also playing a role in the acceleration of intelligent manufacturing. The semiconductor industry is out in front relative to material handling and data automation. However, massive non-semi investment in intelligent manufacturing information technologies is leaving the semi industry lagging far behind.

The use of Big Data, coupled with advanced analytics in the manufacturing process is another area where the semiconductor industry has a long way to go. The amount of data that is needed to be tracked in semiconductor processing is exploding. As design rules shrink to below 32nm critical dimension today and 14nm in the near future, both feature density and the number of transistors per chip experience significant growth. More features per chip translate to:

  • taking more measurements
  • higher lithography refraction rates resulting in higher error rates
  • exceptions requiring more data to resolve and lower yields meaning more excep- tions per wafer (and wafer layer)

As a result, the retention period for these measurements (e.g., to measure tool drift over time) is increased, and the volume of data to be handled by analytics (across lots and tools over time) is magnified considerably. The delayed, but looming transition to 450mm will create a geometric multiplication of the data handling needs.

The value in this massive amount of rapidly created data is in the insight and decision making that can be derived from the data. Here is where the issues lie. Semiconductor manufacturing takes advantage of APC, and in many ways, this is more advanced than a lot of other industries. However, the International Technology Roadmap for Semiconductors (ITRS 2013) emphatically states:

“…a truly comprehensive APC manufacturing strategy is not yet reality, nor is a portfolio of sensors and metrology tools to support complete factory-wide deployment, particularly given the profound changes in materials, processes, and device structures expected for future technology generations. The benefits already realized from APC are driving the development of new sensor technologies and associated control software, which will allow factory-wide comprehensive solutions to be realized in the near future.”

Integrated metrology implementation also presents difficult challenges – metrology tools included as subsystems of process tools. Usually, fabs are designed as a network of tools that each performs one specific function, not multiple functions. This assumption constrains material handling, data flow, MES, etc. Sophisticated, real-time data management and analytics are needed to take advantage of in-situ measurement data with minimal (or zero) impact to tool throughput FIGURE 1 illustrates factory scope and FIGURE 2 shows factory targets as defined by the ITRS.

FIGURE 1. Factory integration scope (Source: ITRS).

FIGURE 1. Factory integration scope (Source: ITRS).

Semi industry Fig 2

FIGURE 2. Factory integration target (Source: ITRS).

Also, in the new “Big Data” section of the ITRS, expected data volumes are shown as “TBD” which is very telling. The units are in Terabytes per day and the possibility that fabs will have to deal with multiples of Petabytes of data is very real. Beyond APC there are other significant data challenges such as traceability to lot and die, test data tracking, predictive tool mainte- nance and Fault Detection and Classification (FDC). The industry is just starting to grapple with how to effectively leverage Big Data and advanced analytics in the semiconductor manufacturing process.

There is a very complex variable interaction problem in semiconductor manufacturing. Going forward, a greater variety of data will be collected at a rapid pace. In many cases, interaction models do not exist today. This will require experimentation and experience to understand interactions in order to derive insight and value from the data. Advanced analytical techniques exist, but determining the right techniques to use for certain decision making will be extremely difficult. Infrastructure and cost are two other issues. The collection, storage and processing of large amounts of data require expensive infrastructure. Support of high data throughput process tool connectivity could require new MES and cell controller architectures. Security is also an issue. Sharing data with capital equipment suppliers and other suppliers will be necessary to derive decision-making value from the data. However this data is highly sensitive and closely guarded by the fab. Similarly, the medical industry is challenged with how to share data aggregated from patient medical records with device makers whose focus is improving patient outcomes in a way that protects patient confidentiality.

Not all the challenges fall solely on the fabs. Capital equipment suppliers have an opportunity to leverage their process and measurement tools to develop solutions to help solve the Big Data, analytics challenges of their customers – the fab operators. Understanding by these suppliers of the environment in which their tools reside will be critical. The system software that runs these tools also becomes more important. The continued development of new process controllers and add-on sensors may require an updated system design paradigm. The data acquisition and management systems of these platforms also need a fresh vision – one that can be implemented in their process and material handling control architectures. Capital equipment suppliers will need to rethink their system design and potentially their business models to leverage the value of the data that their tools can provide.


Semiconductor manufacturing, driven by the need for clean processing and Moore’s Law, leads most other manufacturing sectors in implementing automation and advanced process control. However, large, well-known manufacturing companies outside of semi are making huge investments to progress the use of advanced information technologies in manufacturing because they realize the advantages to be gained. Leveraging technologies capable of handling large amounts of data will provide deeper insights into their manufacturing processes.

The semiconductor industry is poised to take advantage of advanced information technologies. Yes, there is a long way to go and challenges abound. However, the potential value to each fab in addressing key operational metrics such as increased yield, reduced cycle time and increased throughput is significant. The sheer complexity of the interactions of variables in the semiconductor process and the massive amount of data to be collected, stored and analyzed are significant challenges. And, the eventual move to 450mm will compound the huge data volume and velocity issues. I believe that the solution is a collaborative approach – not only fab operators working with software solution providers deploying fab systems, but also in close collaboration with capital equipment suppliers.

Capital equipment suppliers must provide advanced analytical systems that leverage data generated by their tools to help their fab customers address the challenges of Big Data and advanced analytics. It is these companies, who understand best the process data that the equipment can track, interpret and communicate. The semiconductor industry has a long history of fab companies working with their suppliers to further the goals of the industry as a whole (e.g., SEMI standards and other consortia). This effective collaboration model can be used to leverage advanced information technol- ogies for improving the manufacturing process. Semi is lagging, but innovation, drive to success attitude, and organization of the industry will make up the ground quickly.

TOM MARIANO is Executive Vice President and General Manager, Foliage, Burlington, MA

Fast and predictive 3D resist compact models are needed for OPC applications. A methodology to build such models is described, starting from a 3D bulk image, and including resist interface effects such as diffusion. 

BY WOLFGANG DEMMERLE, THOMAS SCHMÖLLER, HUA SONG and JIM SHIELY, Synopsys, Aschheim, Germany, Mountain View, CA and Hillsboro, OR. 

With further shrinking dimensions in advanced semiconductor integrated device manufacturing, 3D effects become increasingly important. Transistor architecture is being extended into the third dimension, such as in FinFETs [1], multi-patterning techniques are adding complexity to lithographic imaging in combination with substrate topography.

Even on planar wafer stacks, process control gets more and more challenging for the 1X nm technology node, as features are being scaled down while exposure conditions remain at 193nm immersion lithography with 1.35 NA. Image contrast decreases, especially at defocus, resulting in high susceptibility for resist loss height and tapered sidewalls; resist profiles may deviate significantly from ideality. Although imaging conditions can be well controlled at nominal exposure conditions, the effect on the process window is usually substantial, as the useful depth of focus as become comparable to the resist film thickness. These dependencies are illustrated in FIGURE 1.

FIGURE 1. Extending 193nm immersion technology to the 1x technology node reveals new patterning challenges.

FIGURE 1. Extending 193nm immersion technology to the 1x technology node reveals new patterning challenges.

Especially random 2D layout structures exhibit weak image areas, where often severe resist top loss or footing occurs, which can results in critical defects within the subsequent etch process. An example for such a weak spot is shown in FIGURE 2a, taken during the early phase of process development [2]. The left clip shows a top-down SEM image of the pattern in resist, taken after the development step. It does not provide any indication for a potential defect in this area. Conventional 2D models represent well the bottom contour of the resist profile. Overlaying the model contour (red line) with the SEM image shows a very good correlation with reality, again giving no motive to apply any layout corrections. However, after etch a bridging hot spot is revealed, as can be seen on right SEM image. A more detailed analysis of the weak spot area using rigorous simulations indicates a low image contrast and severe resist loss of about 60% at the critical location, as shown in FIGURE 2b. Degenerated 3D resist profiles are one of the main root causes for post-etch hotspots at advanced technology nodes.

FIGURE 2. “Weak lithography spot” often becomes only visible after etch if 2D models are used for correction and verification.

FIGURE 2. “Weak lithography spot” often becomes only visible after etch if 2D models are used for correction and verification.

In case those “weak litho spots” in a layout are known, localized corrections to mask features can be applied to prevent yield loss. However, the diversity of random logic structures in advanced designs makes is mandatory that compact models are available which reflect the 3D nature of the resist profiles at any location within the chip, and that this information is being utilized during optical proximity correction and verification, on full chip scale. Rigorously tuned compact models provide an efficient approach to achieve this goal, as we are going outline in the subsequent sections.

Efficient generation of 3D resist compact models

The fundamentals of 3D resist simulation are well captured by rigorous lithography process simulation which is based on a first principle physical modeling approach [3 – 6]. The corresponding simulation results do not only provide an accurate representation of the expected 3D resist profile for arbitrary device patterns within a random layout context. Rigorous models are also capable of predicting the impact of process variations such as focus or dose shifts, wafer stack or illumination condition changes, to only name a few, onto the lithographic performance. This predictive power is achieved by properly separating the various contributions to pattern formation inside the models, for instance addressing optical effects and resist effects individually. Due to their physical nature, the accuracy of optical simulations is only limited by the quality of the input data charactering the optical conditions in the exposure tool. As chemical processes in the photo resist are rather complex, the corresponding models utilize a small set of free, physically or chemically motivated parameters. Only a few experimental data points, e.g. from SEM metrology, are required to calibrate those free parameters, ensuring a good match between experiment and simulation over a wide application space. However, this predictive simulation power comes at the expense of run time – the enormous demand for computational resources does not allow rigorous models at to be applied on a full chip scale.

Standard full chip mask synthesis applications such as optical proximity correction (OPC) or verification are based on the deployment of conventional 2D compact models, i.e. models which represent the resist contours visible in a top-down views. Compact models are optimized for performance. Their accuracy, i.e. the match between model and experiment, is usually achieved by optimizing a large set of fitting parameters, inputting an even larger metrology data set based on CD-SEM measurements. Expansions to a models application space, e.g. to cover additional feature types, are enabled by extending the training data set for model fitting. However, this approach has limitations, as the effort for gathering additional metrology data might become prohibitive, which is rather cogent in the case of 3D metrology.

However, as outlined above, 3D models are required to capture hotspots which are being introduced through local resist height loss. An obvious extension into the third, vertical dimension could be to build individual 2D models at different image depths, representing resist contours of a 3D profile at discrete resist heights. The application of any of the individual 2D models to downstream OPC/LRC tools is straight-forward. However, the relevant image depths need be determined in advance due to the discrete nature of the methodology itself. The critical resist heights can be predetermined, based on etch process results. In practice, a bottom model along with one or two models at critical heights are usually sufficient to detect sites where etch results become sensitive to resist profile. Then the models are directly calibrated on those critical resist heights [7].

One major challenge to support this compact model calibration approach is the preparation of the corresponding metrology data. Conventional, single plane 2D models already require a significant amount of top-down CD-SEM data based on a feature set large enough to represent the entire design space. However, only very rough estimations can be made about the actual resist profiles. This is not sufficient for a reliable 3D model calibration.

Several techniques are available to experimentally characterize the three-dimensional shape of a resist profile, such as atomic force microscope (AFM) or CD-SEM cross section measurements. Common to all these methods is that they are very complex, elaborate, and costly, and therefore not suitable for high volume metrology data collection.

Alternatively, a carefully calibrated rigorous simulator model can be used to generate virtual 3D resist profile data by outputting CD values at specific heights, for specific features. Due to the underlying physical modeling approach, only significantly less experimental data are required for resist model calibration, compared to compact model building [8]. A typical calibration data set consists of CD-SEM top down measurements on a small set of 1D structures, covering critical CDs and pitches, through process window. In addition, a few 3D reference data points, e.g. from AFM, cross section measurements, or etch finger- prints are used to tune the absolute resist height of the profiles in order to match experiment and simulations in all dimensions. This approach not only removes the potential risk of measurement inconsistency between 2D and 3D metrology results, but also opens the door for extensive data collecting with minimum fab efforts.

The CD data sets, either experimentally determined virtually generated for a number of discrete heights, is then fed to compact model calibration at multiple imaging planes. The calibration can be independent for each height. It is often found that fitting a separate threshold for each resist height enables a better match between input data and compact model results. This is mainly due to the fact that vertical resist physics, such as z-diffusion, out-diffusion at boundaries are not included in the traditional compact modeling approach. Differences are compensated through a variable threshold. In addition, other resist models parameters may also be varied to compensate the z-direction physical effects. As a result, the common physicality of the model is compromised, as over-fitting takes place.

In order to demonstrate these dependencies, rigorous simulations based on a calibrated resist model were used to generate reference CD data for over 500 gauges at 9 height positions in the resist film. The gauges represent real fab process covering both 1 dimensional and 2 dimensional layout patterns. The process settings between compact model (ProGen) and rigorous model (S-Litho) are matched exactly. FIGURE 3a shows the results of a compact model calibration in which threshold and common resist model param- eters were kept constant for all sampling heights. The example profile (left image) shows a clear mismatch between the two modeling approaches, which results in an overall matching error with a root-mean-square (RMS) value of 2.9nm for the entire data set (right image).

FIGURE 3. Matching 3D resist compact model profiles to rigorous reference data.

FIGURE 3. Matching 3D resist compact model profiles to rigorous reference data.

These limitations have been overcome by adopting more physical modeling approaches, as used in rigorous simulators, while keeping the model form compact for full-chip applications. To that end, the bulk image is calculated by using one set of retained Hopkins kernels. Optical intensity can be assessed at any image depth without accuracy compromise. Based on an accurate bulk image, the model has been extended to capture effects present in chemically amplified resists. For instance, acid generation, acid-base neutralization, and lateral as well as vertical diffusion are taking into account. Specific boundary conditions at the resist interfaces are used to account for surface effects. The model is formulated in a continuous form so that a model slice at any image depth is readily available for use after calibration. While the calibration data is collected at discrete image planes, all planes are calibrated simultaneously using one set of resist parameters to guarantee physical commonality among them. Moreover, the calibration is done stepwise carefully to ensure the optical part to account for optical effects and resist model to account for resist effects.

The corresponding results are shown in FIGURE 3b. The compact modeling approach now takes vertical diffusion effects into account, including out-diffusion at resist top and bottom, which ensures an excellent match for individual profiles (left image) as well as for the entire data set, resulting in an rms value of 0.5nm.

Compact resist model portability

The integration of physical effects into compact modeling does not only enable the extension of resist simulation into the third, i.e. the vertical dimension, as described in the previous section. Characteristics such as “portability” or “separability,” usually assigned to rigorous models only, become now available within compact modeling as well. Rather than lumping optical and resist effects into a single set of model fitting parameters, the optical set is characterized individually, and resist effects are modeled individually, and therefore separated from the optical contributions to the modeling result. The more clean the separation, the more accurate is the modeling of the resist system response to slight modified optical condition, i.e. conditions different from the ones present during calibration.

Typical simple changes to the optical setup are the variation of focus and exposure dose. FIGURE 4 shows the 3D profile results for two representative features nominal CD of 60 nm (Figure 4(a)) and a wide line with a nominal CD of 200 nm (Figure 4(b)). The calibration 4, center images), with profiles being sampled at various heights. In order to test compact model prediction, we have applied a negative focus offset (Figure 4, left images), and a positive focus offset (right images), and compared the compact model results to profiles determined by rigorous simulation, which served as a reference. The profile changes through focus are very well captured by the compact model, especially the resist top loss at positive defocus (Figure 4, right images). These results are already a first demonstration of predictive power which comes with rigorously tuned compact models. In similar experiments, we have also successfully shown that this modeling concept can be utilized to investigate unintended printing of sub resolution assist features by analyzing the 3D resist response [9], and to source variations [10].

FIGURE 4. Rigorously tuned 3D resist compact models can predict the impact of process variation on profiles without additional data fitting.

FIGURE 4. Rigorously tuned 3D resist compact models can predict the impact of process variation on profiles without additional data fitting.

3D resist model based proximity correction

An accurate and predictive 3D resist compact model can be deployed in mask synthesis verification, or lithographic rule check (LRC), to detect weaknesses in resist profiles. For severe hot spots, simple OPC retargeting is not sufficient to mitigate issues caused by degraded resist profiles. In such a case, the appli- cation of rigorously tuned 3D compact models within optical proximity correction (OPC) offers an efficient approach to automatically repair hotspots within the mask synthesis flow. ProGen models exhibit the unique property of being consistently applicable in combination with different mask correction approaches, for instance conventional OPC as well as inverse lithog- raphy technology (ILT).

FIGURE 5a shows such a weak spot on an ILT mask where the correction is based on a 2D resist compact model, just the contours representing the bottom of the resist profile (black contour). However, the 3D rigorous simulation results reveals severe resist pinching at the top of the resist bulk, as displayed in Figures 5b. Looking at the bottom contour alone, such a hotspot would not have been detected. The red contour in Figure 5a represents the corresponding 3D compact model result extracted at the resist top, confirming the rigorous simulation result. Consequently, in order to achieve a more robust mask solution, we are now taking information from the entire resist profile into the ILT cost function to compute the corresponding correction. The results are shown in Figure 5(c), including bottom resist contour (black) and top resist contour (red) for the modified mask. Although the resist profile sidewall that the location of the weak spot still show some taping, the situation has significant improved over the 2D model based correction. This is confirmed by the rigorous simulation results in Figure 5(d), which does not show indications for resist pinching anymore.

FIGURE 5. Successful OPC correction of an ILT mask, based on 3D resist compact model input.

FIGURE 5. Successful OPC correction of an ILT mask, based on 3D resist compact model input.

The above OPC results conducted by ILT using 3D resist models again imply that resist profile weakness can be corrected in a mask synthesis process with the help of one predictive, accurate 3D resist compact model. As a result, wafer yields will be greatly improved.

Summary and outlook

In this work, we have outlined the concept of using a rigorous simulation approach to tune and improve compact modeling capabilities. Characteristics such as “productivity,” “portability” or “separability,” usually known only within the context of physical models, can be transferred to compact models and therefore made available for full chip mask synthesis applications. We have successfully demonstrated this approach by establishing rigorously tuned 3D resist compact models. Those models combine the performance benefit of compact models, required for full chip mask synthesis applications, with the 3D modeling capabilities and predictivity of rigorous models. We have demonstrated that the rigorously tuned resist model can be carried to a different lithography process setup, e.g. a different illumination source without suffering any accuracy degradation. Those models can be deployed in downstream mask synthesis applications such as optical proximity correction or verification without further modifications. As an example, we have performed a 3D resist model assisted mask correction, using ILT, to mitigate potential post etch hotspotsThe concept of “rigorously tuned compact models” can be easily extended to address other simulation challenges, even beyond the litho process, as shown in FIGURE 6. In fact, it has already been used to improve mask topography simulation capabilities in compact models, or extend resist modeling properties to capture effects which are characteristic to negative tone development. We are currently working on utilizing TCAD physical etch simulation to tune etch compact models, which will take simulated 3D resist profiles as input. A combination of TCAD etch tools and rigorous litho simulation can be used to generate compact models which take underlying wafer topography into account.

FIGURE 6. Extending the concept of “rigorous tuning” to process simulation beyond traditional lithography.

FIGURE 6. Extending the concept of “rigorous tuning” to process simulation beyond traditional lithography.

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BY TOM QUAN, Deputy Director, TSMC

The Prophets of Doom greet every new process node with a chorus of dire warnings about the end of scaling, catastrophic thermal effects, parasitics run amok and . . . you know the rest. The fact that they have been wrong for decades has not diminished their enthusiasm for criticism, and we should expect to hear from them again with the move to 10nm design.

Like any advanced technology transition, 10nm will be challenging, but we need it to happen. Design and process innovation march hand in hand to fuel the remarkable progress of the worldwide electronics industry, clearly demonstrated by the evolution of mobile phones since their introduction (FIGURE 1).

FIGURE 1. The evolution of mobile phones since their introduction.

FIGURE 1. The evolution of mobile phones since their introduction.

Each generation gets harder. There are two different sets of challenges included with a new process node: the process technology issues and the ecosystem issues.

Process technology challenges include:

  • Lithography: continue to scale to 193nm immersion
  • Device: continue to deliver 25-30% speed gain at the same or reduced power
  • Interconnect: address escalating parasitics
  • Production: ramp volume in time to meet end-customer demand
  • Integration of multiple technologies for future systems

Ecosystem challenges include:

  • Quality: optimize design trade-off to best utilize technology
  • Complexity: tackle rising technology and design complexity
  • Schedule: shortened development runway to meet product market window

Adding to these challenges at 10nm is that things get a whole lot more expensive, threatening to upset the traditional benefits of Moore’s Law. We can overcome the technical hurdles but at what cost? At 10nm and below from a process point of view, we can provide PPA improvements but development costs will be high so we need to find the best solutions. Every penny will count at 7nm and 10nm.

FIGURE 2. A new design ecosystem collaboration model is needed due to increasing complexity and shrinking development runways.

FIGURE 2. A new design ecosystem collaboration model is needed due to increasing complexity and shrinking development runways.

Design used to be fairly straightforward for a given technology. The best local optimum was also the best overall optimum: shortest wire length is best; best gate-density equates to the best area scaling; designing on best technology results in the best cost. But these rules no longer apply. For example, sub-10nm issues test conventional wisdom since globalized effects can no longer be resolved by localized approaches. Everything has to be co-optimized; to keep PPA scaling at 10nm and beyond requires tighter integration between process, design, EDA and IP. Increasing complexity and shrinking development runways call for a new design ecosystem collaboration model (FIGURE 2).

Our research and pathfinding teams have been working on disruptive new transistor architectures and materials beyond HKMG and FinFET to enable further energy efficient CMOS scaling. In the future, gate-all-around or narrow wire transistor could be the ultimate device structure. High mobility Ge and III-V channel materials are promising for 0.5V and below operations.

Scaling in the sub-10nm era is more challenging and costly than ever, presenting real opportunities for out-of-box thinking and approaches within the design ecosystem. There is also great promise in wafer-level integration of multiple technologies, paving the way for future systems beyond SoC.

A strong, comprehensive and collaborative ecosystem is the best way to unleash our collective power to turn the designer’s vision into reality.

Spending on microwave RF power semiconductors continues to tick upward as the availability of new gallium nitride (GaN) devices for 4 to 18GHz becomes more pervasive. Point-to-point communications, SATCOM, radars of all types, and new industrial/medical applications will all benefit by the introduction of these high-power GaN devices.

“While gallium arsenide (GaAs) devices are presently the backbone of microwave RF power it is gallium nitride that will drive growth going forward,” notes ABI Research director Lance Wilson. “GaN can operate at much higher voltages and at power levels that were difficult or impossible to reach using GaAs.”

In addition to the above mentioned application segments, microwave GaN is finally reaching the performance points that can start to seriously challenge travelling wave tube applications for new designs that have historically used the latter.

“Microwave RF Power Semiconductorsexamines Microwave RF power semiconductor devices with power outputs of greater than 3 watts and those that operate at frequencies of 4 to 18 GHz. This study is part of ABI Research’s ongoing effort to track the major changes in the RF power industry.

This release contains analysis of the six main vertical segments (C-Band GaAs, C-Band GaN, X-Band GaAs, X-Band GaN, Ku-Band GaAs, and Ku-Band GaN) and is further expanded to 28 application sub-segments.

These findings are part of ABI Research’s High-Power RF Active Devices Market Research.

ABI Research provides in-depth analysis and quantitative forecasting of trends in global connectivity and other emerging technologies.

For the first time, SEMICON Europa 2014 will offer two new power-related technical forums — Power Electronics Conference (8-9 October) and Low Power Conference (7-8 October). The exhibition and conferences will offer an in-depth look at the cutting-edge energy technology delivering new levels of energy efficiency in electronics. Energy efficiency is a key challenge and advances in power microelectronics, batteries, mobility, and energy harvesting systems are making power management smarter to reduce energy consumption. SEMICON Europa’s two new Power Conferences focus on how innovators and their technologies are building energy-optimized applications.

The theme of the Low Power Conference is “Highly Energy Efficient Nanotechnologies and Applications.” The number of connected electronics devices is growing exponentially. According to Jean-Marc Chery, COO STMicroelectronics, to sustain this growth, the semiconductor industry needs a real breakthrough in energy efficiency — both for connected devices and for the communication infrastructure. At the same time, the traditional planar bulk CMOS technology is plateauing in power consumption and performance beyond 28nm, so breakthrough solutions for energy efficient systems are mandatory to continue the growth.

Sessions include: Market Analysis; Technology Energy Efficiency; Processors; Energy Efficient Design; Energy Efficient EDA Tools; and Applications.  Speaker highlights include:

  • STMicroelectronics: Jean-Marc Chery, COO
  • GLOBALFOUNDRIES: Manfred Horstmann, director, Products and Integration
  • Qualcomm Technologies: Mustafa Badaroglu, senior program manager
  • Cadence Design Systems, Inc.: Marcus Binning, senior AE manager
  • IBS, Inc.:  Handel Jones, CEO,
  • Hewlett-Packard: Rémi Barbarin, CTO
  • Schneider Electric: Gilles Chabanis, manager, Pervasive Sensing

The Power Electronics Conference  is themed “The Ultimate Path to CO2 Reduction.” Modern power semiconductors play an essential role in energy conservation and worldwide CO2 reduction. Philippe Roussel, business unit manager at Yole Developpement, will present the keynote on market and technology overview of the Power Electronics industry, including a look at the impact of Wide BandGap (WBG) Devices.    He believes that the emergence of new WBG technologies such as SiC and GaN will reshape the established power electronics industry, especially on the high-voltage side.  SiC and GaN offer benefits (higher frequency switching, power density, and more) that may dramatically help improve the power conversion efficiency. Yole believes that this could lead to lower CO2 emission if both SiC and GaN can emerge from labs to mass production. SiC transitioned a few years ago and GaN is starting the commercialization curve. By 2020, WBD devices are expected to generate more than $1 billion according to Yole.

The session highlights include:

  • Applications session — speakers from CEA/LETI, EpiGaN, European Center for Power Electronics e.V. (ECPE), Infineon, European Commission, Renault, and Supergrid Institute.
  • Technology and Materials session — presenters from Fairchild, Infineon Technologies AG, SiCrystal AG, Siltronic AG, Soitec, ST Catania, and Yole Developpement.

For more information on SEMICON Europa, visit www.semiconeuropa.org.

Alpha and Omega Semiconductor Limited, a designer, developer and global supplier of a broad range of power semiconductors and power ICs, today announced that the Board of Directors of AOS has promoted Mr. Yifan Liang, the Interim Chief Financial Officer, to serve as the Chief Financial Officer of AOS, effective immediately.

“We are very pleased that Yifan was promoted to the position of Chief Financial Officer. Yifan has been serving as our Interim Chief Financial Officer since November 2013, and he has been an integral part of AOS’ accounting and finance operations since he joined the Company as Corporate Controller in 2004. As the Interim Chief Financial Officer, Yifan was instrumental in the successful implementation of our business plan to expand revenue growth and profitability. Given his in-depth knowledge of the Company and extensive experiences in accounting and financial matters, he is the ideal person to lead us financially as we continue to execute our business strategies,” said Dr. Mike Chang, the Chairman and Chief Executive Officer.

Prior to his appointment as the Chief Financial Officer, Mr. Liang has served as our Interim Chief Financial Officer and Corporate Secretary since November 2013, and he has served as our Chief Accounting Officer since October 2006 and our Assistant Corporate Secretary from November 2009 to November 2013. Mr. Liang joined our Company in August 2004 as our Corporate Controller. Prior to joining us, Mr. Liang held various positions at PricewaterhouseCoopers LLP, or PwC, from 1995 to 2004, including Audit Manager in PwC’s San Jose office. Mr. Liang received his B.S. in management information system from the People’s University of China and M.A. in finance and accounting from the University of Alabama.

OMRON and Holst Centre/imec have unveiled a prototype of an extremely compact vibrational energy harvesting DC power supply with worlds’ highest efficiency. The prototype will be demonstrated at the TECHNO-FRONTIER2014 exhibition in Tokyo from July 23rd till July 25th. Combining OMRON’s electret energy harvester with a Holst Centre/imec power management IC, it can convert and store energy from vibrations in the µW range with high efficiency to the driving voltage of general sensors. The prototype measures just 5 x 6 cm – with potential to shrink as small as 2 x 2 cm. Its small size, light weight (15.4 gram) and user-variable output voltage are ideal for a wide-range of autonomous wireless sensor node applications in the industrial and consumer domains, particularly in inaccessible locations.

Small, autonomous wireless sensors that can simply be installed and then left to collect and share data are attracting huge interest. They are the foundation of the emerging, Internet of Things. And they could enable new levels of automation and equipment monitoring in industrial applications. The ongoing miniaturization and reduction of power consumption of sensors and microelectronics make these devices possible. However, a key question has been how to power them.

“Energy harvesting – extracting unused or waste energy from the local environment – is perfect for autonomous sensor nodes. It does away with the need for cables and changing batteries, allowing true “fix-and-forget” systems. The combination of OMRON’s robust electrostatic vibration harvester and our efficient power management technology enables an extremely compact design that can be installed in even the most inaccessible places – whereas today’s vibrational harvester power supplies are too large and too heavy,” says René Elfrink, Senior Researcher Sensors & Energy Harvesters at Holst Centre/imec.

“The vibration in the environment of customers are various and volatile. Under such an environment, our harvester can produce energy even just a little. But so far, we could not use our harvester as a stable DC power supply. Before developing this compact vibrational harvesting power supply, we benchmarked power management technologies from many potential partners and found Holst Centre/imec’s offering to be the most mature. The resulting power supply meets all the requirements for small, low-power wireless sensors, particularly industrial applications such has equipment control and predictive maintenance systems,” adds Daido Uchida, General manager of Technology Produce & Start-up division of OMRON Corporation.

Working closely with OMRON, researchers from Holst Centre/imec integrated the electrostatic harvester and power management electronics into a power-optimized module just 5 cm x 6 cm. Initial feedback from potential customers suggests this is already small enough for industrial application. However, the module has potential for further miniaturization down to 2 cm x 2 cm.

The supply’s output can be set to anything between 1.5 V and 5 V, giving users complete flexibility to replace any kind of battery in existing designs or create brand new products. The module contains an ON/OFF signal for efficient duty cycling with low power sensor systems.

OMRON is currently putting the prototype through a number of field tests with customers to gather further input before entering volume production.


The global market outlook for AC-DC and DC-DC power supplies is set for healthy expansion starting this year until at least 2018, with revenue during these four years projected to grow by $3.5 billion, according to a new report from IHS Technology.

Market revenue will expand to $25.1 billion in 2018, up from $21.6 billion in 2014, as presented in the attached figure.

The hefty four-year increase is an improvement compared to the previous three years from 2010 to 2013, when revenue grew by less than $1.0 billion. Growth this year is anticipated at 4.6 percent, with expansion to be as robust or even strengthen in 2015 and 2016.

“The markets for most applications that use a power supply are now growing again after a couple of gloomy years, with emerging applications such as power supplies for light-emitting diode (LED) lighting and media tablets leading the way,” said Jonathon Eykyn, power supply and storage component analyst for IHS. “Demand for power supplies for these two applications alone is projected to grow by more than $2.5 billion from 2014 to 2018, but other power supply markets—such as telecommunications, data communications and industrial—are also projected to provide growth opportunities to power supply vendors in the coming years.”

Aside from emerging applications driving growth, many projects that had been cancelled or postponed because of economic concerns in the past are now being restarted to coincide with new projects and technology rollouts, further stimulating the market. Also fueling significant expansion in the demand for power supplies is the continued growth of data centers to cope with the rise of cloud computing and the Internet of Things. Thanks to such drivers, revenue for power supplies to the server, storage and networking markets is projected to climb 24 percent from 2014 to 2018.

Growth is also solid in the markets for cellphone power supplies, with revenue forecast to ascend more than 8 percent in 2014. However, growth will slow after this year as more phones begin to ship without a bundled charger.

Meanwhile, the power supplies market for desktop PCs and notebooks is calculated to decline by around 2 percent every year from 2014 to 2018. This is because the traditional computing markets of desktop PCs and notebooks are set to deteriorate as consumers continue to favor more mobile solutions, such as media tablets and even cellphones.

All of these changes are influencing the state of the power supply market. In particular, market share rankings for 2013 were turbulent with six of the top 10 manufacturers changing positions and two new companies entering the elite tier. Overall, Delta Electronics retained its position as the world’s largest supplier of merchant power supplies, followed by Emerson and Lite-On.

The two suppliers that grew the most in market share in 2013 were Salcomp and Mean Well, whose combined revenue rose more than 30 percent and added 1.3 percent to their share of market compared to 2012.

“These suppliers are well-entrenched within the fast-growing cellphone and LED lighting markets,” Eykyn said. “It’s clear from these results that other manufacturers will have to continue to diversify their portfolios in order to remain competitive.”

These findings can be found in the forthcoming report, The World Market for AC-DC & DC-DC Merchant Power Supplies from the Power & Energy service of IHS. The full report from IHS includes analysis of the opportunities for commodity AC-DC, as well as non-commodity AC-DC and DC-DC power supplies across 22 applications, with forecasts through 2018. It also presents market-share estimates with 13 separate splits.